[alsa-devel] [PATCH 3/4] ASoC: soc-cache: Add support for LZO register caching

Mark Brown broonie at opensource.wolfsonmicro.com
Thu Nov 4 23:45:58 CET 2010

On Thu, Nov 04, 2010 at 02:22:43PM +0000, Dimitris Papastamos wrote:

This looks really good except for the handling of unsupported register
sizes I mentioend for another patch and the fact that the LZO additions
to Kconfig probably ought to go in here.

> by using the LZO compression technique, one can get down to ~3-5kB.  There
> might be a performance penalty associated with each individual read/write
> due to decompressing/compressing the underlying cache, however that should not

I strongly suspect that there will actually be a performance penalty
associated with the (de-)compress :)  

As we discussed previously this can be mitigated against in future by
keeping the last accessed block of memory uncompressed so that we don't
need to do the LZO operations so often when doing a sequence of accesses
to the same area of the register map (this should work well during DAPM
runs since the power bits tend to all be close together, for example).
Timeouts or a different chunking algorithm could be used to reduce the
memory cost of this, though we need to be careful we don't overengineer.

> be noticeable.  The memory benefits depend on whether the target architecture
> can get rid of the memory occupied by the original register defaults cache
> which is marked as __devinitconst.

Even if it doesn't manage to get rid of the original copy there will of
course still be some memory gain as the runtime allocated register cache
will be compressed - only the size of the win will be affected, there's
no question that there will be some benefit unless the register map is
pathologic and doesn't compress.

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