[alsa-devel] [PATCH] asoc tlv320aic33: skip usage of PLL in some cases
jhnikula at gmail.com
Fri Apr 18 10:58:49 CEST 2008
On Fri, Apr 18, 2008 at 11:13 AM, Daniel Mack <daniel at caiaq.org> wrote:
> Hi Jarkko,
> No, the 256-clock mode is for output only, while in my setup the TLV is
> in slave mode. I attached this chip to the I2S output of an PXA270 which
> always outputs sample rate * 256 as system clock. In this very case, the
> PLL can be bypassed by selecting the left path described on page 27.
Ok, now I see. Probably you should refer it as, at least in comment, 128*Q
instead of 256 eventhough the driver is not currently touching the Q value
> AIC3X_SAMPLE_RATE_SEL_REG defaults to 0 which is what I want in this
> case. Thus, I don't have to write it.
Are you sure this is a general case?
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