[alsa-devel] [PATCH] asoc tlv320aic33: skip usage of PLL in some cases
daniel at caiaq.org
Fri Apr 18 11:38:21 CEST 2008
On Fri, Apr 18, 2008 at 11:58:49AM +0300, Jarkko Nikula wrote:
> > No, the 256-clock mode is for output only, while in my setup the TLV is
> > in slave mode. I attached this chip to the I2S output of an PXA270 which
> > always outputs sample rate * 256 as system clock. In this very case, the
> > PLL can be bypassed by selecting the left path described on page 27.
> Ok, now I see. Probably you should refer it as, at least in comment, 128*Q
> instead of 256 eventhough the driver is not currently touching the Q value
> in AIC3X_PLL_PROGA_REG.
Well, the constraint for that condition is that MCLK = 256*WCLK, and the
reason why that works for the chip without PLL is that Q=2. I stated
that a little better in the attached patch.
> > AIC3X_SAMPLE_RATE_SEL_REG defaults to 0 which is what I want in this
> > case. Thus, I don't have to write it.
> Are you sure this is a general case?
Well, the reset default is 0 (as stated on page 44) and set_hw_params()
is the only location where this value is written. So if it's never
written with a different value, it should always be set to its default,
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