[Sound-open-firmware] [PATCH 1/4] [RFC]DMIC: Add PDM microphones (DMIC) support to DAI

[Seppo Ingalsuo]

On 02.05.2018 19:54, Pierre-Louis Bossart wrote:
> On 5/2/18 10:27 AM, Seppo Ingalsuo wrote:
>>
>>
>> On 02.05.2018 16:43, Pierre-Louis Bossart wrote:
>>>>>> +    /* Calculate CIC shift from the decimation factor specific 
>>>>>> gain.
>>>>>> +     */
>>>>>> +    mcic = cfg->mcic;
>>>>>> +    g_cic = mcic * mcic * mcic * mcic * mcic;
>>>>>
>>>>> yikes, what is this mcic^5 ?
>>>>
>>>> Yep, it's the gain for +1 / -1 PDM bits in CIC decimator part. It's 
>>>> needed to set the scaling HW shifter. It also gives some idea of 
>>>> oversampling ratios to use for a microphone to get some # of bits 
>>>> of resolution as PCM code.
>>>
>>> I meant: where does this ^5 come from? First time i see this sort of 
>>> formula in filter design.
>>
>> I see now -- There's a 5th order integrator-comb filter as 1st 
>> decimation filter stage for the PDM bits. Wikipedia has nowadays 
>> everything:
>>
>> https://en.wikipedia.org/wiki/Cascaded_integrator%E2%80%93comb_filter
>>
>> The high DC gain is caused by the integration part. The 1st equation 
>> with the Sigma statement shows the transfer function. By setting 
>> R=mcic, N=5, omega = 0 the same DC gain formula that I used is achieved.
>
> Do I get this right that this 5 figure is hardware-related and used to 
> figure out the compensation that needs to happens in additional 
> FIR-based processing?

Yes, it's due to 5th order filter in hardware. With CIC based PDM->PCM 
conversion the CIC order needs to be at least equal to typical 
microphones side noise shaper order that's usually fourth order. The 5th 
order CIC ensures the noise shaping created by the microphones above 
audio band will alias only a very little amount.

Since the driver supports several sample rates in range 8 - 96 kHz (*) 
the HW shifter setting need to be computed this way due to varying CIC 
decimation factor. Though the shifter setting could be also a lookup 
table for min..max CIC decimation factor. But since there may be changes 
in hardware revisions maybe the code to calculate the shift is simplest 
to maintain.

Thanks,
Seppo

(*) If suitable integer factors exist for microphone clock divider, CIC 
decimation factor, FIR decimation factor from the platform IO clock 
that's usually 19.2 or 24 MHz


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