[Sound-open-firmware] [PATCH] arch: xtensa: set SRAM window error codes during bootloader

[Liam Girdwood]

From: Kamil Kulesza <kamil.kulesza at linux.intel.com>

Set status (0x05) and error (0x00) code in Memory Window 0 when the bootloader starts.
boot_entry.S - set status (0x05) and error (0x00) code before wnd0 reprogram
platform/memory.h - increase bootloader size

Signed-off-by: Kamil Kulesza <kamil.kulesza at linux.intel.com>
---
 src/arch/xtensa/boot_entry.S                  | 22 +++++++++++++++++++
 .../apollolake/include/platform/memory.h      |  2 +-
 .../cannonlake/include/platform/memory.h      |  2 +-
 3 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/src/arch/xtensa/boot_entry.S b/src/arch/xtensa/boot_entry.S
index 72d0e5e..5ebba16 100644
--- a/src/arch/xtensa/boot_entry.S
+++ b/src/arch/xtensa/boot_entry.S
@@ -81,6 +81,18 @@ wnd0_base_val:
 wnd0_size_val:
 	.word HP_SRAM_WIN0_SIZE | 0x7
 
+wnd0_status_address:
+	.word HP_SRAM_WIN0_BASE
+
+wnd0_error_address:
+	.word HP_SRAM_WIN0_BASE | 0x4
+
+fw_loaded_status_value:
+	.word	0x00000005
+
+fw_no_errors_value:
+	.word	0x00000000
+
 boot_init:
 	.align 4
 #if defined(PLATFORM_DISABLE_L2CACHE_AT_BOOT)
@@ -101,6 +113,16 @@ boot_init:
 	l32r	a3, sof_stack_base
 	mov		sp, a3
 
+	/* set status register to 0x00000005 in wnd0 */
+	l32r	a3,	fw_loaded_status_value
+	l32r	a5,	wnd0_status_address
+	s32i	a3, a5, 0
+
+	/* set error register to 0x00 in wnd0 */
+	l32r	a3, fw_no_errors_value
+	l32r	a5,	wnd0_error_address
+	s32i	a3, a5, 0
+
 	/* realloc memory window0 to
 	continue reporting boot progress */
 	l32r	a3, wnd0_size
diff --git a/src/platform/apollolake/include/platform/memory.h b/src/platform/apollolake/include/platform/memory.h
index 390b31b..6d4ea1b 100644
--- a/src/platform/apollolake/include/platform/memory.h
+++ b/src/platform/apollolake/include/platform/memory.h
@@ -348,7 +348,7 @@
 
 /* boot loader in IMR */
 #define IMR_BOOT_LDR_TEXT_ENTRY_BASE	0xB000A000
-#define IMR_BOOT_LDR_TEXT_ENTRY_SIZE	0x66
+#define IMR_BOOT_LDR_TEXT_ENTRY_SIZE	0x86
 #define IMR_BOOT_LDR_LIT_BASE		(IMR_BOOT_LDR_TEXT_ENTRY_BASE + \
 					IMR_BOOT_LDR_TEXT_ENTRY_SIZE)
 #define IMR_BOOT_LDR_LIT_SIZE		0x70
diff --git a/src/platform/cannonlake/include/platform/memory.h b/src/platform/cannonlake/include/platform/memory.h
index 85e7996..f1a8aa5 100644
--- a/src/platform/cannonlake/include/platform/memory.h
+++ b/src/platform/cannonlake/include/platform/memory.h
@@ -353,7 +353,7 @@
 #define IMR_BOOT_LDR_MANIFEST_SIZE	0x6000
 
 #define IMR_BOOT_LDR_TEXT_ENTRY_BASE	0xB0038000
-#define IMR_BOOT_LDR_TEXT_ENTRY_SIZE	0x66
+#define IMR_BOOT_LDR_TEXT_ENTRY_SIZE	0x86
 #define IMR_BOOT_LDR_LIT_BASE		(IMR_BOOT_LDR_TEXT_ENTRY_BASE + IMR_BOOT_LDR_TEXT_ENTRY_SIZE)
 #define IMR_BOOT_LDR_LIT_SIZE		0x20
 #define IMR_BOOT_LDR_TEXT_BASE		(IMR_BOOT_LDR_LIT_BASE + IMR_BOOT_LDR_LIT_SIZE)
-- 
2.17.0