[Sound-open-firmware] [PATCH_V2] BDW: init HW registers at setup time

[Rander Wang]

Signed-off-by: Rander Wang <rander.wang at linux.intel.com>

---
V2: remove unused code in ssp setting

test it on Broadwell, no need to test other platforms

SOF: master 131a1887631621
kernel: v4.14 d09db67c5a9d6d
SOF-tools: master 13b56fa6047c566a
---
 src/drivers/hsw-ssp.c                        |  5 -----
 src/platform/haswell/include/platform/shim.h |  3 ++-
 src/platform/haswell/platform.c              | 18 ++++++++++++++++++
 3 files changed, 20 insertions(+), 6 deletions(-)

diff --git a/src/drivers/hsw-ssp.c b/src/drivers/hsw-ssp.c
index b2fa99e..43024a4 100644
--- a/src/drivers/hsw-ssp.c
+++ b/src/drivers/hsw-ssp.c
@@ -102,9 +102,6 @@ static inline int ssp_set_config(struct dai *dai,
 
 	trace_ssp("cos");
 
-	/* unset free running clock */
-	shim_update_bits(SHIM_CSR2, SHIM_CSR2_SFCR_SSP(dai->index), 0);
-
 	/* disable clock */
 	shim_update_bits(SHIM_CLKCTL, SHIM_CLKCTL_EN_SSP(dai->index), 0);
 
@@ -405,8 +402,6 @@ static inline int ssp_set_config(struct dai *dai,
 	/* enable free running clock */
 	ssp_update_bits(dai, SSCR0, SSCR0_SSE, SSCR0_SSE);
 	ssp_update_bits(dai, SSCR0, SSCR0_SSE, 0);
-	shim_update_bits(SHIM_CSR2, SHIM_CSR2_SFCR_SSP(dai->index),
-			 SHIM_CSR2_SFCR_SSP(dai->index));
 
 out:
 	spin_unlock(&ssp->lock);
diff --git a/src/platform/haswell/include/platform/shim.h b/src/platform/haswell/include/platform/shim.h
index 62f047a..fefaec9 100644
--- a/src/platform/haswell/include/platform/shim.h
+++ b/src/platform/haswell/include/platform/shim.h
@@ -57,10 +57,12 @@
 #define SHIM_CSR_STALL		(0x1 << 10)
 #define SHIM_CSR_SDPM0          (0x1 << 11)
 #define SHIM_CSR_SDPM1          (0x1 << 12)
+#define SHIM_CSR_PCE		(0x1 << 15)
 #define SHIM_CSR_SFCR0          (0x1 << 27)
 #define SHIM_CSR_SFCR1          (0x1 << 28)
 #define SHIM_CSR_DCS(x)         (x << 4)
 #define SHIM_CSR_DCS_MASK       (0x7 << 4)
+#define SHIM_CSR_SFCR_SSP(x)	(1 << (27 + x))
 
 /*  ISRX 0x18 */
 #define SHIM_ISRX_BUSY		(0x1 << 1)
@@ -100,7 +102,6 @@
 /* CSR2 / CS2 */
 #define SHIM_CSR2_SDFD_SSP0	(1 << 1)
 #define SHIM_CSR2_SDFD_SSP1	(1 << 2)
-#define SHIM_CSR2_SFCR_SSP(x)	(1 << (27 + x))
 
 /* LTRC */
 #define SHIM_LTRC_VAL(x)		(x << 0)
diff --git a/src/platform/haswell/platform.c b/src/platform/haswell/platform.c
index 8d8dbc7..81ce67a 100644
--- a/src/platform/haswell/platform.c
+++ b/src/platform/haswell/platform.c
@@ -221,6 +221,23 @@ void platform_interrupt_unmask(uint32_t irq, uint32_t mask)
 	}
 }
 
+/* init shim registers */
+static void platform_init_shim(void)
+{
+	/* disable power gate */
+	io_reg_update_bits(SHIM_BASE + SHIM_CLKCTL,
+			   SHIM_CLKCTL_DCPLCG,
+			   SHIM_CLKCTL_DCPLCG);
+
+	/* disable parity check */
+	io_reg_update_bits(SHIM_BASE + SHIM_CSR, SHIM_CSR_PCE, 0);
+
+	/* enable DMA finsh on ssp ports */
+	io_reg_update_bits(SHIM_BASE + SHIM_CSR2,
+			   SHIM_CSR2_SDFD_SSP0 | SHIM_CSR2_SDFD_SSP1,
+			   SHIM_CSR2_SDFD_SSP0 | SHIM_CSR2_SDFD_SSP1);
+}
+
 int platform_init(struct sof *sof)
 {
 	struct dma *dmac0;
@@ -234,6 +251,7 @@ int platform_init(struct sof *sof)
 	bzero((void*)MAILBOX_BASE, IPC_MAX_MAILBOX_BYTES);
 
 	trace_point(TRACE_BOOT_PLATFORM_SHIM);
+	platform_init_shim();
 
 	trace_point(TRACE_BOOT_PLATFORM_CLOCK);
 	init_platform_clocks();
-- 
2.14.1