[Sound-open-firmware] [PATCH] platform: cnl: Add cannonlake platform headers
Liam Girdwood
liam.r.girdwood at linux.intel.com
Tue Jan 23 17:40:13 CET 2018
From: Rander Wang <rander.wang at linux.intel.com>
Add platform headers for Intel Cannonlake platform.
Signed-off-by: Rander Wang <rander.wang at linux.intel.com>
---
.../cannonlake/include/platform/Makefile.am | 9 +
src/platform/cannonlake/include/platform/clk.h | 44 +++
src/platform/cannonlake/include/platform/dma.h | 72 +++++
.../cannonlake/include/platform/interrupt.h | 171 ++++++++++
src/platform/cannonlake/include/platform/mailbox.h | 84 +++++
src/platform/cannonlake/include/platform/memory.h | 348 +++++++++++++++++++++
.../cannonlake/include/platform/platform.h | 142 +++++++++
src/platform/cannonlake/include/platform/shim.h | 274 ++++++++++++++++
src/platform/cannonlake/include/platform/timer.h | 72 +++++
9 files changed, 1216 insertions(+)
create mode 100644 src/platform/cannonlake/include/platform/Makefile.am
create mode 100644 src/platform/cannonlake/include/platform/clk.h
create mode 100644 src/platform/cannonlake/include/platform/dma.h
create mode 100644 src/platform/cannonlake/include/platform/interrupt.h
create mode 100644 src/platform/cannonlake/include/platform/mailbox.h
create mode 100644 src/platform/cannonlake/include/platform/memory.h
create mode 100644 src/platform/cannonlake/include/platform/platform.h
create mode 100644 src/platform/cannonlake/include/platform/shim.h
create mode 100644 src/platform/cannonlake/include/platform/timer.h
diff --git a/src/platform/cannonlake/include/platform/Makefile.am b/src/platform/cannonlake/include/platform/Makefile.am
new file mode 100644
index 0000000..4e4e20d
--- /dev/null
+++ b/src/platform/cannonlake/include/platform/Makefile.am
@@ -0,0 +1,9 @@
+noinst_HEADERS = \
+ clk.h \
+ dma.h \
+ interrupt.h \
+ mailbox.h \
+ memory.h \
+ platform.h \
+ shim.h \
+ timer.h
diff --git a/src/platform/cannonlake/include/platform/clk.h b/src/platform/cannonlake/include/platform/clk.h
new file mode 100644
index 0000000..d6ccd6c
--- /dev/null
+++ b/src/platform/cannonlake/include/platform/clk.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2017, Intel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the Intel Corporation nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Liam Girdwood <liam.r.girdwood at linux.intel.com>
+ * Keyon Jie <yang.jie at linux.intel.com>
+ * Rander Wang <rander.wang at intel.com>
+ */
+
+#ifndef __PLATFORM_CLOCK__
+#define __PLATFORM_CLOCK__
+
+#define CLK_CPU 0
+#define CLK_SSP 1
+
+#define CLK_DEFAULT_CPU_HZ 120000000
+#define CLK_MAX_CPU_HZ 400000000
+
+void init_platform_clocks(void);
+
+#endif
diff --git a/src/platform/cannonlake/include/platform/dma.h b/src/platform/cannonlake/include/platform/dma.h
new file mode 100644
index 0000000..00dcda8
--- /dev/null
+++ b/src/platform/cannonlake/include/platform/dma.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2017, Intel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the Intel Corporation nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Liam Girdwood <liam.r.girdwood at linux.intel.com>
+ * Keyon Jie <yang.jie at linux.intel.com>
+ * Rander Wang <rander.wang at intel.com>
+ */
+
+#ifndef __PLATFORM_DMA_H__
+#define __PLATFORM_DMA_H__
+
+/* available DMACs */
+#define DMA_GP_LP_DMAC0 0
+#define DMA_GP_LP_DMAC1 1
+#define DMA_GP_HP_DMAC0 2
+#define DMA_GP_HP_DMAC1 3
+#define DMA_HOST_IN_DMAC 4
+#define DMA_HOST_OUT_DMAC 5
+#define DMA_LINK_IN_DMAC 6
+#define DMA_LINK_OUT_DMAC 7
+
+/* mappings - TODO improve API to get type */
+#define DMA_ID_DMAC0 DMA_HOST_IN_DMAC
+#define DMA_ID_DMAC1 DMA_GP_LP_DMAC0
+#define DMA_ID_DMAC2 DMA_HOST_OUT_DMAC
+#define DMA_ID_DMAC3 DMA_GP_HP_DMAC0
+#define DMA_ID_DMAC4 DMA_GP_LP_DMAC1
+#define DMA_ID_DMAC5 DMA_GP_HP_DMAC1
+#define DMA_ID_DMAC6 DMA_LINK_IN_DMAC
+#define DMA_ID_DMAC7 DMA_LINK_OUT_DMAC
+
+/* handshakes */
+#define DMA_HANDSHAKE_DMIC_CH0 0
+#define DMA_HANDSHAKE_DMIC_CH1 1
+#define DMA_HANDSHAKE_SSP0_TX 2
+#define DMA_HANDSHAKE_SSP0_RX 3
+#define DMA_HANDSHAKE_SSP1_TX 4
+#define DMA_HANDSHAKE_SSP1_RX 5
+#define DMA_HANDSHAKE_SSP2_TX 6
+#define DMA_HANDSHAKE_SSP2_RX 7
+#define DMA_HANDSHAKE_SSP3_TX 8
+#define DMA_HANDSHAKE_SSP3_RX 9
+#define DMA_HANDSHAKE_SSP4_TX 10
+#define DMA_HANDSHAKE_SSP4_RX 11
+#define DMA_HANDSHAKE_SSP5_TX 12
+#define DMA_HANDSHAKE_SSP5_RX 13
+
+#endif
diff --git a/src/platform/cannonlake/include/platform/interrupt.h b/src/platform/cannonlake/include/platform/interrupt.h
new file mode 100644
index 0000000..4735ddc
--- /dev/null
+++ b/src/platform/cannonlake/include/platform/interrupt.h
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2017, Intel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the Intel Corporation nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Liam Girdwood <liam.r.girdwood at linux.intel.com>
+ * Keyon Jie <yang.jie at linux.intel.com>
+ * Rander Wang <rander.wang at intel.com>
+ */
+
+#ifndef __INCLUDE_PLATFORM_INTERRUPT__
+#define __INCLUDE_PLATFORM_INTERRUPT__
+
+#include <stdint.h>
+#include <reef/interrupt-map.h>
+
+#define PLATFORM_IRQ_CHILDREN 32
+
+/* IRQ numbers - wrt Tensilica DSP */
+#define IRQ_NUM_SOFTWARE0 0 /* level 1 */
+#define IRQ_NUM_TIMER1 1 /* level 1 */
+#define IRQ_NUM_EXT_LEVEL1 2 /* level 1 */
+#define IRQ_NUM_SOFTWARE2 3 /* level 1 */
+#define IRQ_NUM_SOFTWARE3 4 /* level 2 */
+#define IRQ_NUM_TIMER2 5 /* level 2 */
+#define IRQ_NUM_EXT_LEVEL2 6 /* level 2 */
+#define IRQ_NUM_SOFTWARE4 7 /* level 2 */
+#define IRQ_NUM_SOFTWARE5 8 /* level 3 */
+#define IRQ_NUM_TIMER3 9 /* level 3 */
+#define IRQ_NUM_EXT_LEVEL3 10 /* level 3 */
+#define IRQ_NUM_SOFTWARE6 11 /* level 3 */
+#define IRQ_NUM_SOFTWARE7 12 /* level 4 */
+#define IRQ_NUM_EXT_LEVEL4 13 /* level 4 */
+#define IRQ_NUM_SOFTWARE8 14 /* level 4 */
+#define IRQ_NUM_SOFTWARE9 15 /* level 5 */
+#define IRQ_NUM_EXT_LEVEL5 16 /* level 5 */
+#define IRQ_NUM_EXT_LEVEL6 17 /* level 5 */
+#define IRQ_NUM_EXT_LEVEL7 18 /* level 5 */
+#define IRQ_NUM_SOFTWARE10 19 /* level 5 */
+#define IRQ_NUM_NMI 20 /* level 7 */
+
+/* IRQ Level 2 bits */
+#define IRQ_BIT_LVL2_HP_GP_DMA0(x) (x + 24)
+#define IRQ_BIT_LVL2_WALL_CLK1 23
+#define IRQ_BIT_LVL2_WALL_CLK0 22
+#define IRQ_BIT_LVL2_L2_MEMERR 21
+#define IRQ_BIT_LVL2_SHA256 16
+#define IRQ_BIT_LVL2_L2_CACHE 15
+#define IRQ_BIT_LVL2_IDC 8
+#define IRQ_BIT_LVL2_HOST_IPC 7
+#define IRQ_BIT_LVL2_CSME_IPC 6
+#define IRQ_BIT_LVL2_PMC_IPC 5
+
+/* IRQ Level 3 bits */
+#define IRQ_BIT_LVL3_CODE_LOADER 31
+#define IRQ_BIT_LVL3_HOST_STREAM_OUT(x) (16 + x)
+#define IRQ_BIT_LVL3_HOST_STREAM_IN(x) (0 + x)
+
+/* IRQ Level 4 bits */
+#define IRQ_BIT_LVL4_LINK_STREAM_OUT(x) (16 + x)
+#define IRQ_BIT_LVL4_LINK_STREAM_IN(x) (0 + x)
+
+/* IRQ Level 5 bits */
+#define IRQ_BIT_LVL5_LP_GP_DMA1 15
+#define IRQ_BIT_LVL5_LP_GP_DMA0 16
+#define IRQ_BIT_LVL5_DMIC 6
+#define IRQ_BIT_LVL5_SSP(x) (0 + x)
+
+/* Level 2 Peripheral IRQ mappings */
+#define IRQ_EXT_HP_GPDMA_LVL2(xcpu) \
+ REEF_IRQ(IRQ_BIT_LVL2_HP_GP_DMA0(0), 2, xcpu, IRQ_NUM_EXT_LEVEL2)
+#define IRQ_EXT_IDC_LVL2(xcpu) \
+ REEF_IRQ(IRQ_BIT_LVL2_IDC, 2, xcpu, IRQ_NUM_EXT_LEVEL2)
+#define IRQ_EXT_IPC_LVL2(xcpu) \
+ REEF_IRQ(IRQ_BIT_LVL2_HOST_IPC, 2, xcpu, IRQ_NUM_EXT_LEVEL2)
+#define IRQ_EXT_TSTAMP1_LVL2(xcpu) \
+ REEF_IRQ(IRQ_BIT_LVL2_WALL_CLK1, 2, xcpu, IRQ_NUM_EXT_LEVEL2)
+#define IRQ_EXT_TSTAMP0_LVL2(xcpu) \
+ REEF_IRQ(IRQ_BIT_LVL2_WALL_CLK0, 2, xcpu, IRQ_NUM_EXT_LEVEL2)
+#define IRQ_EXT_MERR_LVL2(xcpu) \
+ REEF_IRQ(IRQ_BIT_LVL2_L2_MEMERR, 2, xcpu, IRQ_NUM_EXT_LEVEL2)
+#define IRQ_EXT_L2CACHE_LVL2(xcpu) \
+ REEF_IRQ(IRQ_BIT_LVL2_L2_CACHE, 2, xcpu, IRQ_NUM_EXT_LEVEL2)
+#define IRQ_EXT_SHA256_LVL2(xcpu) \
+ REEF_IRQ(IRQ_BIT_LVL2_SHA256, 2, xcpu, IRQ_NUM_EXT_LEVEL2)
+
+/* Level 3 Peripheral IRQ mappings */
+#define IRQ_EXT_CODE_DMA_LVL3(xcpu) \
+ REEF_IRQ(IRQ_BIT_LVL3_CODE_LOADER, 3, xcpu, IRQ_NUM_EXT_LEVEL3)
+#define IRQ_EXT_HOST_DMA_IN_LVL3(xcpu, channel) \
+ REEF_IRQ(IRQ_BIT_LVL3_HOST_STREAM_IN(channel), 3, xcpu, IRQ_NUM_EXT_LEVEL3)
+#define IRQ_EXT_HOST_DMA_OUT_LVL3(xcpu, channel) \
+ REEF_IRQ(IRQ_BIT_LVL3_HOST_STREAM_OUT(channel), 3, xcpu, IRQ_NUM_EXT_LEVEL3)
+
+/* Level 4 Peripheral IRQ mappings */
+#define IRQ_EXT_LINK_DMA_IN_LVL4(xcpu, channel) \
+ REEF_IRQ(IRQ_BIT_LVL4_LINK_STREAM_IN(channel), 4, xcpu, IRQ_NUM_EXT_LEVEL4)
+#define IRQ_EXT_LINK_DMA_OUT_LVL4(xcpu, channel) \
+ REEF_IRQ(IRQ_BIT_LVL4_LINK_STREAM_OUT(channel), 4, xcpu, IRQ_NUM_EXT_LEVEL4)
+
+/* Level 5 Peripheral IRQ mappings */
+#define IRQ_EXT_LP_GPDMA0_LVL5(xcpu, channel) \
+ REEF_IRQ(IRQ_BIT_LVL5_LP_GP_DMA0, 5, xcpu, IRQ_NUM_EXT_LEVEL5)
+#define IRQ_EXT_LP_GPDMA1_LVL4(xcpu, channel) \
+ REEF_IRQ(IRQ_BIT_LVL5_LP_GP_DMA1, 4, xcpu, IRQ_NUM_EXT_LEVEL4)
+#define IRQ_EXT_SSP0_LVL5(xcpu) \
+ REEF_IRQ(IRQ_BIT_LVL5_SSP(0), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
+#define IRQ_EXT_SSP1_LVL5(xcpu) \
+ REEF_IRQ(IRQ_BIT_LVL5_SSP(1), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
+#define IRQ_EXT_SSP2_LVL5(xcpu) \
+ REEF_IRQ(IRQ_BIT_LVL5_SSP(2), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
+#define IRQ_EXT_SSP3_LVL5(xcpu) \
+ REEF_IRQ(IRQ_BIT_LVL5_SSP(3), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
+#define IRQ_EXT_DMIC_LVL5(xcpu) \
+ REEF_IRQ(IRQ_BIT_LVL5_DMIC, 5, xcpu, IRQ_NUM_EXT_LEVEL5)
+
+
+/* IRQ Masks */
+#define IRQ_MASK_SOFTWARE0 (1 << IRQ_NUM_SOFTWARE0)
+#define IRQ_MASK_TIMER1 (1 << IRQ_NUM_TIMER1)
+#define IRQ_MASK_EXT_LEVEL1 (1 << IRQ_NUM_EXT_LEVEL1)
+#define IRQ_MASK_SOFTWARE1 (1 << IRQ_NUM_SOFTWARE1)
+#define IRQ_MASK_SOFTWARE2 (1 << IRQ_NUM_SOFTWARE2)
+#define IRQ_MASK_TIMER2 (1 << IRQ_NUM_TIMER2)
+#define IRQ_MASK_EXT_LEVEL2 (1 << IRQ_NUM_EXT_LEVEL2)
+#define IRQ_MASK_SOFTWARE3 (1 << IRQ_NUM_SOFTWARE3)
+#define IRQ_MASK_SOFTWARE4 (1 << IRQ_NUM_SOFTWARE4)
+#define IRQ_MASK_TIMER3 (1 << IRQ_NUM_TIMER3)
+#define IRQ_MASK_EXT_LEVEL3 (1 << IRQ_NUM_EXT_LEVEL3)
+#define IRQ_MASK_SOFTWARE5 (1 << IRQ_NUM_SOFTWARE5)
+#define IRQ_MASK_SOFTWARE6 (1 << IRQ_NUM_SOFTWARE6)
+#define IRQ_MASK_EXT_LEVEL4 (1 << IRQ_NUM_EXT_LEVEL4)
+#define IRQ_MASK_SOFTWARE7 (1 << IRQ_NUM_SOFTWARE7)
+#define IRQ_MASK_SOFTWARE8 (1 << IRQ_NUM_SOFTWARE8)
+#define IRQ_MASK_EXT_LEVEL5 (1 << IRQ_NUM_EXT_LEVEL5)
+#define IRQ_MASK_EXT_LEVEL6 (1 << IRQ_NUM_EXT_LEVEL6)
+#define IRQ_MASK_EXT_LEVEL7 (1 << IRQ_NUM_EXT_LEVEL7)
+#define IRQ_MASK_SOFTWARE9 (1 << IRQ_NUM_SOFTWARE9)
+
+void platform_interrupt_init(void);
+
+struct irq_parent *platform_irq_get_parent(uint32_t irq);
+void platform_interrupt_set(int irq);
+void platform_interrupt_clear(uint32_t irq, uint32_t mask);
+uint32_t platform_interrupt_get_enabled(void);
+void platform_interrupt_mask(uint32_t irq, uint32_t mask);
+void platform_interrupt_unmask(uint32_t irq, uint32_t mask);
+
+#endif
diff --git a/src/platform/cannonlake/include/platform/mailbox.h b/src/platform/cannonlake/include/platform/mailbox.h
new file mode 100644
index 0000000..6724fe5
--- /dev/null
+++ b/src/platform/cannonlake/include/platform/mailbox.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2017, Intel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the Intel Corporation nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Liam Girdwood <liam.r.girdwood at linux.intel.com>
+ * Keyon Jie <yang.jie at linux.intel.com>
+ * Rander Wang <rander.wang at intel.com>
+ */
+
+#ifndef __INCLUDE_PLATFORM_MAILBOX__
+#define __INCLUDE_PLATFORM_MAILBOX__
+
+#include <platform/memory.h>
+
+
+/*
+ * The Window Region on Broxton HPSRAM is organised like this :-
+ * +--------------------------------------------------------------------------+
+ * | Offset | Region | Size |
+ * +---------------------+----------------+-----------------------------------+
+ * | SRAM_TRACE_BASE | Trace Buffer W3| SRAM_TRACE_SIZE |
+ * +---------------------+----------------+-----------------------------------+
+ * | SRAM_DEBUG_BASE | Debug data W2 | SRAM_DEBUG_SIZE |
+ * +---------------------+----------------+-----------------------------------+
+ * | SRAM_INBOX_BASE | Inbox W1 | SRAM_INBOX_SIZE |
+ * +---------------------+----------------+-----------------------------------+
+ * | SRAM_OUTBOX_BASE | Outbox W0 | SRAM_MAILBOX_SIZE |
+ * +---------------------+----------------+-----------------------------------+
+ * | SRAM_SW_REG_BASE | SW Registers W0| SRAM_SW_REG_SIZE |
+ * +---------------------+----------------+-----------------------------------+
+ */
+
+/* window 3 - trace */
+#define MAILBOX_TRACE_SIZE SRAM_TRACE_SIZE
+#define MAILBOX_TRACE_BASE SRAM_TRACE_BASE
+
+/* window 2 debug and exception */
+#define MAILBOX_DEBUG_SIZE (SRAM_DEBUG_SIZE - MAILBOX_EXCEPTION_SIZE)
+#define MAILBOX_DEBUG_BASE SRAM_DEBUG_BASE
+
+#define MAILBOX_EXCEPTION_SIZE 0x100
+#define MAILBOX_EXCEPTION_BASE \
+ (MAILBOX_DEBUG_BASE + MAILBOX_DEBUG_SIZE)
+
+/* window 1 inbox/downlink and FW registers */
+#define MAILBOX_HOSTBOX_SIZE SRAM_INBOX_SIZE
+#define MAILBOX_HOSTBOX_BASE SRAM_INBOX_BASE
+
+
+#define MAILBOX_STREAM_SIZE 0x200
+#define MAILBOX_STREAM_BASE \
+ (MAILBOX_BASE + MAILBOX_STREAM_OFFSET)
+
+/* window 0 */
+#define MAILBOX_DSPBOX_SIZE SRAM_OUTBOX_SIZE
+#define MAILBOX_DSPBOX_BASE SRAM_OUTBOX_BASE
+
+#define MAILBOX_SW_REG_SIZE SRAM_SW_REG_SIZE
+#define MAILBOX_SW_REG_BASE SRAM_SW_REG_BASE
+
+#endif
diff --git a/src/platform/cannonlake/include/platform/memory.h b/src/platform/cannonlake/include/platform/memory.h
new file mode 100644
index 0000000..06b27f3
--- /dev/null
+++ b/src/platform/cannonlake/include/platform/memory.h
@@ -0,0 +1,348 @@
+/*
+ * Copyright (c) 2017, Intel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the Intel Corporation nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Liam Girdwood <liam.r.girdwood at linux.intel.com>
+ * Keyon Jie <yang.jie at linux.intel.com>
+ * Rander Wang <rander.wang at intel.com>
+ */
+
+#ifndef __PLATFORM_MEMORY_H__
+#define __PLATFORM_MEMORY_H__
+
+#include <config.h>
+
+/* physical DSP addresses */
+
+/* shim */
+#define SHIM_BASE 0x00071F00
+#define SHIM_SIZE 0x00000100
+
+/* cmd IO to audio codecs */
+#define CMD_BASE 0x00001100
+#define CMD_SIZE 0x00000010
+
+/* resource allocation */
+#define RES_BASE 0x00001110
+#define RES_SIZE 0x00000010
+
+/* IPC to the host */
+#define IPC_HOST_BASE 0x00071E00
+#define IPC_HOST_SIZE 0x00000020
+
+/* intra DSP IPC */
+#define IPC_DSP_SIZE 0x00000080
+#define IPC_DSP_BASE(x) (0x00001200 + x * IPC_DSP_SIZE)
+
+/* SRAM window for HOST */
+#define HOST_WIN_SIZE 0x00000008
+#define HOST_WIN_BASE(x) (0x00071A00 + x * HOST_WIN_SIZE)
+
+/* IRQ controller */
+#define IRQ_BASE 0x00078800
+#define IRQ_SIZE 0x00000200
+
+/* time stamping */
+#define TIME_BASE 0x00071800
+#define TIME_SIZE 0x00000200
+
+/* M/N dividers */
+#define MN_BASE 0x00078C00
+#define MN_SIZE 0x00000200
+
+/* low power DMA position */
+#define LP_GP_DMA_LINK_SIZE 0x00000080
+#define LP_GP_DMA_LINK_BASE(x) (0x00001C00 + x * LP_GP_DMA_LINK_SIZE)
+
+/* high performance DMA position */
+#define HP_GP_DMA_LINK_SIZE 0x00000800
+#define HP_GP_DMA_LINK_BASE(x) (0x00001D00 + x * HP_GP_DMA_LINK_SIZE)
+
+/* link DMAC stream */
+#define GTW_LINK_OUT_STREAM_SIZE 0x00000020
+#define GTW_LINK_OUT_STREAM_BASE(x) \
+ (0x00072400 + x * GTW_LINK_OUT_STREAM_SIZE)
+
+#define GTW_LINK_IN_STREAM_SIZE 0x00000020
+#define GTW_LINK_IN_STREAM_BASE(x) \
+ (0x00072600 + x * GTW_LINK_IN_STREAM_SIZE)
+
+/* host DMAC stream */
+#define GTW_HOST_OUT_STREAM_SIZE 0x00000040
+#define GTW_HOST_OUT_STREAM_BASE(x) \
+ (0x00072800 + x * GTW_HOST_OUT_STREAM_SIZE)
+
+#define GTW_HOST_IN_STREAM_SIZE 0x00000040
+#define GTW_HOST_IN_STREAM_BASE(x) \
+ (0x00072C00 + x * GTW_HOST_IN_STREAM_SIZE)
+
+/* code loader */
+#define GTW_CODE_LDR_SIZE 0x00000040
+#define GTW_CODE_LDR_BASE 0x00002BC0
+
+/* L2 TLBs */
+#define L2_HP_SRAM_TLB_SIZE 0x00001000
+#define L2_HP_SRAM_TLB_BASE 0x00003000
+
+/* DMICs */
+#define DMIC_BASE 0x00004000
+#define DMIC_SIZE 0x00004000
+
+/* SSP */
+#define SSP_BASE(x) (0x00077000 + x * SSP_SIZE)
+#define SSP_SIZE 0x0000200
+
+/* low power DMACs */
+#define LP_GP_DMA_SIZE 0x00001000
+#define LP_GP_DMA_BASE(x) (0x0007C000 + x * LP_GP_DMA_SIZE)
+
+/* high performance DMACs */
+#define HP_GP_DMA_SIZE 0x00001000
+#define HP_GP_DMA_BASE(x) (0x0000E000 + x * HP_GP_DMA_SIZE)
+
+/* ROM */
+#define ROM_BASE 0xBEFE0000
+#define ROM_SIZE 0x00002000
+
+#define TEXT_BASE 0xb0039000
+#define TEXT_LENGTH 0xB000
+#define DATA_BASE 0xb0044000
+#define DATA_LENGTH 0x4000
+
+
+/*
+ * The HP SRAM Region on Cannonlake is organised like this :-
+ * +--------------------------------------------------------------------------+
+ * | Offset | Region | Size |
+ * +---------------------+----------------+-----------------------------------+
+ * | SRAM_SW_REG_BASE | SW Registers W0| SRAM_SW_REG_SIZE |
+ * +---------------------+----------------+-----------------------------------+
+ * | SRAM_OUTBOX_BASE | Outbox W0 | SRAM_MAILBOX_SIZE |
+ * +---------------------+----------------+-----------------------------------+
+ * | SRAM_INBOX_BASE | Inbox W1 | SRAM_INBOX_SIZE |
+ * +---------------------+----------------+-----------------------------------+
+ * | SRAM_DEBUG_BASE | Debug data W2 | SRAM_DEBUG_SIZE |
+ * +---------------------+----------------+-----------------------------------+
+ * | SRAM_TRACE_BASE | Trace Buffer W3| SRAM_TRACE_SIZE |
+ * +---------------------+----------------+-----------------------------------+
+ * | HP_SRAM_BASE | DMA | HEAP_HP_BUFFER_SIZE |
+ * +---------------------+----------------+-----------------------------------+
+ * | HEAP_SYSTEM_BASE | System Heap | HEAP_SYSTEM_SIZE |
+ * +---------------------+----------------+-----------------------------------+
+ * | HEAP_RUNTIME_BASE | Runtime Heap | HEAP_RUNTIME_SIZE |
+ * +---------------------+----------------+-----------------------------------+
+ * | HEAP_BUFFER_BASE | Module Buffers | HEAP_BUFFER_SIZE |
+ * +---------------------+----------------+-----------------------------------+
+ * | REEF_STACK_END | Stack | REEF_STACK_SIZE |
+ * +---------------------+----------------+-----------------------------------+
+ * | REEF_STACK_BASE | | |
+ * +---------------------+----------------+-----------------------------------+
+ */
+
+/* HP SRAM */
+#define HP_SRAM_BASE 0xBE000000
+#define HP_SRAM_SIZE 0x002F0000
+
+/* HP SRAM Base */
+#define HP_SRAM_VECBASE_RESET (HP_SRAM_BASE + 0x40000)
+
+/* Heap section sizes for module pool */
+#define HEAP_RT_COUNT8 0
+#define HEAP_RT_COUNT16 256
+#define HEAP_RT_COUNT32 128
+#define HEAP_RT_COUNT64 64
+#define HEAP_RT_COUNT128 32
+#define HEAP_RT_COUNT256 16
+#define HEAP_RT_COUNT512 8
+#define HEAP_RT_COUNT1024 4
+
+/* text and data share the same L2 SRAM on Cannonlake */
+#define REEF_TEXT_START 0xBE040400
+#define REEF_TEXT_START_SIZE 0x40
+#define L2_VECTOR_SIZE 0x1000
+
+/* HP SRAM windows */
+/* window 0 */
+#define SRAM_SW_REG_BASE (HP_SRAM_BASE + 0x4000)
+#define SRAM_SW_REG_SIZE 0x1000
+
+#define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE)
+#define SRAM_OUTBOX_SIZE 0x1000
+
+/* window 1 */
+#define SRAM_INBOX_BASE (SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE)
+#define SRAM_INBOX_SIZE 0x2000
+
+/* window 2 */
+#define SRAM_DEBUG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE)
+#define SRAM_DEBUG_SIZE 0x1000
+
+/* window 3 */
+#define SRAM_TRACE_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE)
+#define SRAM_TRACE_SIZE 0x2000
+
+#define HP_SRAM_WIN0_BASE SRAM_SW_REG_BASE
+#define HP_SRAM_WIN0_SIZE (SRAM_SW_REG_SIZE + SRAM_OUTBOX_SIZE)
+#define HP_SRAM_WIN1_BASE SRAM_INBOX_BASE
+#define HP_SRAM_WIN1_SIZE SRAM_INBOX_SIZE
+#define HP_SRAM_WIN2_BASE SRAM_DEBUG_BASE
+#define HP_SRAM_WIN2_SIZE SRAM_DEBUG_SIZE
+#define HP_SRAM_WIN3_BASE SRAM_TRACE_BASE
+#define HP_SRAM_WIN3_SIZE SRAM_TRACE_SIZE
+
+#define HEAP_DMA_BUFFER_BASE (SRAM_TRACE_BASE + SRAM_TRACE_SIZE)
+#define HEAP_DMA_BUFFER_SIZE 0x20000
+#define HEAP_DMA_BUFFER_BLOCK_SIZE 0x180
+#define HEAP_DMA_BUFFER_COUNT \
+ (HEAP_DMA_BUFFER_SIZE / HEAP_DMA_BUFFER_BLOCK_SIZE)
+
+#define REEF_TEXT_BASE (REEF_TEXT_START + REEF_TEXT_START_SIZE)
+#define REEF_TEXT_SIZE 0x18000
+
+/* initialized data */
+#define REEF_DATA_SIZE 0x18000
+
+/* bss data */
+#define REEF_BSS_DATA_SIZE 0x8000
+
+/* Heap configuration */
+#define HEAP_SYSTEM_BASE (REEF_TEXT_BASE + REEF_TEXT_SIZE + \
+ REEF_DATA_SIZE + REEF_BSS_DATA_SIZE)
+
+#define HEAP_SYSTEM_SIZE 0x8000
+
+#define HEAP_RUNTIME_BASE (HEAP_SYSTEM_BASE + HEAP_SYSTEM_SIZE)
+#define HEAP_RUNTIME_SIZE \
+ (HEAP_RT_COUNT8 * 8 + HEAP_RT_COUNT16 * 16 + \
+ HEAP_RT_COUNT32 * 32 + HEAP_RT_COUNT64 * 64 + \
+ HEAP_RT_COUNT128 * 128 + HEAP_RT_COUNT256 * 256 + \
+ HEAP_RT_COUNT512 * 512 + HEAP_RT_COUNT1024 * 1024)
+
+/* Stack configuration */
+#define REEF_STACK_SIZE 0x2000
+#define REEF_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE)
+#define REEF_STACK_END (REEF_STACK_BASE - REEF_STACK_SIZE)
+
+#define HEAP_BUFFER_BASE (HEAP_RUNTIME_BASE + HEAP_RUNTIME_SIZE)
+#define HEAP_BUFFER_SIZE \
+ (REEF_STACK_END - HEAP_BUFFER_BASE)
+#define HEAP_BUFFER_BLOCK_SIZE 0x180
+#define HEAP_BUFFER_COUNT (HEAP_BUFFER_SIZE / HEAP_BUFFER_BLOCK_SIZE)
+
+/*
+ * The LP SRAM Heap and Stack on Cannonlake are organised like this :-
+ *
+ * +--------------------------------------------------------------------------+
+ * | Offset | Region | Size |
+ * +---------------------+----------------+-----------------------------------+
+ * | LP_SRAM_BASE | RO Data | REEF_LP_DATA_SIZE |
+ * | | Data | |
+ * | | BSS | |
+ * +---------------------+----------------+-----------------------------------+
+ * | HEAP_LP_SYSTEM_BASE | System Heap | HEAP_LP_SYSTEM_SIZE |
+ * +---------------------+----------------+-----------------------------------+
+ * | HEAP_LP_RUNTIME_BASE| Runtime Heap | HEAP_LP_RUNTIME_SIZE |
+ * +---------------------+----------------+-----------------------------------+
+ * | HEAP_LP_BUFFER_BASE | Module Buffers | HEAP_LP_BUFFER_SIZE |
+ * +---------------------+----------------+-----------------------------------+
+ * | REEF_LP_STACK_END | Stack | REEF_LP_STACK_SIZE |
+ * +---------------------+----------------+-----------------------------------+
+ * | REEF_STACK_BASE | | |
+ * +---------------------+----------------+-----------------------------------+
+ */
+
+/* LP SRAM */
+#define LP_SRAM_BASE 0xBE800000
+#define LP_SRAM_SIZE 0x00020000
+
+/* Heap section sizes for module pool */
+#define HEAP_RT_LP_COUNT8 0
+#define HEAP_RT_LP_COUNT16 256
+#define HEAP_RT_LP_COUNT32 128
+#define HEAP_RT_LP_COUNT64 64
+#define HEAP_RT_LP_COUNT128 32
+#define HEAP_RT_LP_COUNT256 16
+#define HEAP_RT_LP_COUNT512 8
+#define HEAP_RT_LP_COUNT1024 4
+
+/* Heap configuration */
+#define REEF_LP_DATA_SIZE 0x4000
+
+#define HEAP_LP_SYSTEM_BASE (LP_SRAM_BASE + REEF_LP_DATA_SIZE)
+#define HEAP_LP_SYSTEM_SIZE 0x1000
+
+#define HEAP_LP_RUNTIME_BASE (HEAP_LP_SYSTEM_BASE + HEAP_LP_SYSTEM_SIZE)
+#define HEAP_LP_RUNTIME_SIZE \
+ (HEAP_RT_LP_COUNT8 * 8 + HEAP_RT_LP_COUNT16 * 16 + \
+ HEAP_RT_LP_COUNT32 * 32 + HEAP_RT_LP_COUNT64 * 64 + \
+ HEAP_RT_LP_COUNT128 * 128 + HEAP_RT_LP_COUNT256 * 256 + \
+ HEAP_RT_LP_COUNT512 * 512 + HEAP_RT_LP_COUNT1024 * 1024)
+
+#define HEAP_LP_BUFFER_BASE (HEAP_LP_RUNTIME_BASE + HEAP_LP_RUNTIME_SIZE)
+#define HEAP_LP_BUFFER_SIZE \
+ (LP_SRAM_SIZE - HEAP_LP_RUNTIME_SIZE - REEF_LP_STACK_SIZE - HEAP_LP_SYSTEM_SIZE)
+
+#define HEAP_LP_BUFFER_BLOCK_SIZE 0x180
+#define HEAP_LP_BUFFER_COUNT (HEAP_LP_BUFFER_SIZE / HEAP_LP_BUFFER_BLOCK_SIZE)
+
+
+/* Stack configuration */
+#define REEF_LP_STACK_SIZE 0x1000
+#define REEF_LP_STACK_BASE (LP_SRAM_BASE + LP_SRAM_SIZE)
+#define REEF_LP_STACK_END (REEF_LP_STACK_BASE - REEF_LP_STACK_SIZE)
+
+
+/* Vector and literal sizes - not in core-isa.h */
+#define REEF_MEM_VECT_LIT_SIZE 0x8
+#define REEF_MEM_VECT_TEXT_SIZE 0x38
+#define REEF_MEM_VECT_SIZE (REEF_MEM_VECT_TEXT_SIZE + REEF_MEM_VECT_LIT_SIZE)
+
+#define REEF_MEM_ERROR_TEXT_SIZE 0x180
+#define REEF_MEM_ERROR_LIT_SIZE 0x8
+
+#define REEF_MEM_RESET_TEXT_SIZE 0x268
+#define REEF_MEM_RESET_LIT_SIZE 0x8
+#define REEF_MEM_VECBASE_LIT_SIZE 0x178
+
+#define REEF_MEM_RO_SIZE 0x8
+
+/* boot loadee in IMR */
+#define IMR_BOOT_LDR_TEXT_ENTRY_BASE 0xB0038000
+#define IMR_BOOT_LDR_TEXT_ENTRY_SIZE 0x40
+#define IMR_BOOT_LDR_LIT_BASE (IMR_BOOT_LDR_TEXT_ENTRY_BASE + IMR_BOOT_LDR_TEXT_ENTRY_SIZE)
+#define IMR_BOOT_LDR_LIT_SIZE 0x70
+#define IMR_BOOT_LDR_TEXT_BASE (IMR_BOOT_LDR_LIT_BASE + IMR_BOOT_LDR_LIT_SIZE)
+#define IMR_BOOT_LDR_TEXT_SIZE 0x1C00
+#define IMR_BOOT_LDR_TEXT1_BASE (IMR_BOOT_LDR_TEXT_BASE + IMR_BOOT_LDR_TEXT_SIZE)
+#define IMR_BOOT_LDR_TEXT1_SIZE 0x2000
+#define IMR_BOOT_LDR_DATA_BASE 0xB0002000
+#define IMR_BOOT_LDR_DATA_SIZE 0x1000
+#define IMR_BOOT_LDR_BSS_BASE 0xB0100000
+#define IMR_BOOT_LDR_BSS_SIZE 0x10000
+#define IMR_BOOT_LDR_MANIFEST_BASE 0xB0032000
+#define IMR_BOOT_LDR_MANIFEST_SIZE 0x6000
+
+#endif
diff --git a/src/platform/cannonlake/include/platform/platform.h b/src/platform/cannonlake/include/platform/platform.h
new file mode 100644
index 0000000..00e0069
--- /dev/null
+++ b/src/platform/cannonlake/include/platform/platform.h
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2017, Intel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the Intel Corporation nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Liam Girdwood <liam.r.girdwood at linux.intel.com>
+ * Keyon Jie <yang.jie at linux.intel.com>
+ * Rander Wang <rander.wang at intel.com>
+ */
+
+#ifndef __PLATFORM_PLATFORM_H__
+#define __PLATFORM_PLATFORM_H__
+
+#include <platform/shim.h>
+#include <platform/interrupt.h>
+#include <uapi/ipc.h>
+
+struct reef;
+
+#define PLATFORM_SSP_COUNT 3
+
+/* Host page size */
+#define HOST_PAGE_SIZE 4096
+#define PLATFORM_PAGE_TABLE_SIZE 256
+
+/* IPC Interrupt */
+#define PLATFORM_IPC_INTERUPT IRQ_EXT_IPC_LVL2(0)
+
+/* pipeline IRQ */
+#define PLATFORM_SCHEDULE_IRQ IRQ_NUM_SOFTWARE5
+
+#define PLATFORM_IRQ_TASK_HIGH IRQ_NUM_SOFTWARE4
+#define PLATFORM_IRQ_TASK_MED IRQ_NUM_SOFTWARE3
+#define PLATFORM_IRQ_TASK_LOW IRQ_NUM_SOFTWARE2
+
+#define PLATFORM_SCHEDULE_COST 200
+
+/* maximum preload pipeline depth */
+#define MAX_PRELOAD_SIZE 20
+
+/* DMA treats PHY addresses as host address unless within DSP region */
+#define PLATFORM_HOST_DMA_MASK 0x00000000
+
+/* Platform stream capabilities */
+#define PLATFORM_MAX_CHANNELS 4
+#define PLATFORM_MAX_STREAMS 5
+
+/* clock source used by scheduler for deadline calculations */
+#define PLATFORM_SCHED_CLOCK CLK_SSP
+
+/* DMA channel drain timeout in microseconds - TODO: caclulate based on topology */
+#define PLATFORM_DMA_TIMEOUT 1333
+
+/* DMA host transfer timeouts in microseconds */
+#define PLATFORM_HOST_DMA_TIMEOUT 50
+
+/* WorkQ window size in microseconds */
+#define PLATFORM_WORKQ_WINDOW 2000
+
+/* platform WorkQ clock */
+#define PLATFORM_WORKQ_CLOCK CLK_SSP
+
+/* Host finish work schedule delay in microseconds */
+#define PLATFORM_HOST_FINISH_DELAY 100
+
+/* Host finish work(drain from host to dai) timeout in microseconds */
+#define PLATFORM_HOST_FINISH_TIMEOUT 50000
+
+// TODO: move to SW reg header
+#define SW_REG_STATUS 0x0
+#define SW_REG_ERRCODE 0x04
+
+/* local buffer size of DMA tracing */
+#define DMA_TRACE_LOCAL_SIZE HOST_PAGE_SIZE
+
+/* the interval of DMA trace copying */
+#define DMA_TRACE_PERIOD 500000
+
+/*
+ * the interval of reschedule DMA trace copying in special case like half
+ * fullness of local DMA trace buffer
+ */
+#define DMA_TRACE_RESCHEDULE_TIME 5000
+
+/* DMAC used for trace DMA */
+#define PLATFORM_TRACE_DMAC DMA_ID_DMAC0
+
+/* DSP should be idle in this time frame */
+#define PLATFORM_IDLE_TIME 750000
+
+/* Platform defined panic code */
+#define platform_panic(__x) \
+ sw_reg_write(SW_REG_STATUS, (0xdead000 | __x) & 0x3fffffff)
+
+/* Platform defined trace code */
+#if USE_SW_REG_STATUS
+#define platform_trace_point(__x) \
+ sw_reg_write(SW_REG_STATUS, (0xace0000 | __x) & 0x3fffffff));\
+ sw_reg_write(SW_REG_ERRCODE, __x)
+#else //using SW_REG_STATUS may influence the ROM status, don't do that atm.
+#define platform_trace_point(__x) \
+ sw_reg_write(SW_REG_ERRCODE, __x)
+#endif
+
+struct timer *platform_timer;
+
+/*
+ * APIs declared here are defined for every platform and IPC mechanism.
+ */
+
+int platform_boot_complete(uint32_t boot_message);
+
+int platform_init(struct reef *reef);
+
+int platform_ssp_set_mn(uint32_t ssp_port, uint32_t source, uint32_t rate,
+ uint32_t bclk_fs);
+
+void platform_ssp_disable_mn(uint32_t ssp_port);
+
+#endif
diff --git a/src/platform/cannonlake/include/platform/shim.h b/src/platform/cannonlake/include/platform/shim.h
new file mode 100644
index 0000000..6654335
--- /dev/null
+++ b/src/platform/cannonlake/include/platform/shim.h
@@ -0,0 +1,274 @@
+/*
+ * Copyright (c) 2017, Intel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the Intel Corporation nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Liam Girdwood <liam.r.girdwood at linux.intel.com>
+ * Keyon Jie <yang.jie at linux.intel.com>
+ * Rander Wang <rander.wang at intel.com>
+ */
+
+#ifndef __PLATFORM_SHIM_H__
+#define __PLATFORM_SHIM_H__
+
+#include <platform/memory.h>
+
+#ifndef ASSEMBLY
+#include <stdint.h>
+#endif
+
+/* DSP IPC for Host Registers */
+#define IPC_DIPCTDR 0x00
+#define IPC_DIPCTDA 0x04
+#define IPC_DIPCTDD 0x08
+#define IPC_DIPCIDR 0x10
+#define IPC_DIPCIDA 0x14
+#define IPC_DIPCIDD 0x18
+#define IPC_DIPCCTL 0x28
+
+
+/* DIPCTDR */
+#define IPC_DIPCTDR_BUSY (1 << 31)
+#define IPC_DIPCTDR_MSG_MASK 0x7FFFFFFF
+
+/* DIPCTDA */
+#define IPC_DIPCTDA_BUSY (1 << 31)
+#define IPC_DIPCTDA_MSG_MASK 0x7FFFFFFF
+
+/* DIPCTE */
+#define IPC_DIPCTE_MSG_MASK 0x3FFFFFFF
+
+/* DIPCIDA*/
+#define IPC_DIPCIDA_DONE (1 << 31)
+
+/* DIPCIE */
+#define IPC_DIPCIE_DONE (1 << 31)
+#define IPC_DIPCIE_MSG_MASK 0x3FFFFFFF
+
+/* DIPCCTL */
+#define IPC_DIPCCTL_IPCIDIE (1 << 1)
+#define IPC_DIPCCTL_IPCTBIE (1 << 0)
+
+#define IRQ_CPU_OFFSET 0x40
+
+#define REG_IRQ_IL2MSD(xcpu) (0x0 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL2MCD(xcpu) (0x4 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL2MD(xcpu) (0x8 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL2SD(xcpu) (0xc + (xcpu * IRQ_CPU_OFFSET))
+
+/* all mask valid bits */
+#define REG_IRQ_IL2MD_ALL 0x03F181F0
+
+#define REG_IRQ_IL3MSD(xcpu) (0x10 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL3MCD(xcpu) (0x14 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL3MD(xcpu) (0x18 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL3SD(xcpu) (0x1c + (xcpu * IRQ_CPU_OFFSET))
+
+/* all mask valid bits */
+#define REG_IRQ_IL3MD_ALL 0x807F81FF
+
+#define REG_IRQ_IL4MSD(xcpu) (0x20 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL4MCD(xcpu) (0x24 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL4MD(xcpu) (0x28 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL4SD(xcpu) (0x2c + (xcpu * IRQ_CPU_OFFSET))
+
+/* all mask valid bits */
+#define REG_IRQ_IL4MD_ALL 0x807F81FF
+
+#define REG_IRQ_IL5MSD(xcpu) (0x30 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL5MCD(xcpu) (0x34 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL5MD(xcpu) (0x38 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL5SD(xcpu) (0x3c + (xcpu * IRQ_CPU_OFFSET))
+
+/* all mask valid bits */
+#define REG_IRQ_IL5MD_ALL 0xFFFFC0CF
+
+#define REG_IRQ_IL2RSD 0x100
+#define REG_IRQ_IL3RSD 0x104
+#define REG_IRQ_IL4RSD 0x108
+#define REG_IRQ_IL5RSD 0x10c
+
+#define REG_IRQ_LVL5_LP_GPDMA0_MASK (0xff << 16)
+#define REG_IRQ_LVL5_LP_GPDMA1_MASK (0xff << 24)
+
+/* DSP Shim Registers */
+#define SHIM_DSPWC 0x20 /* DSP Wall Clock */
+#define SHIM_DSPWCTCS 0x28 /* DSP Wall Clock Timer Control & Status */
+#define SHIM_DSPWCT0C 0x30 /* DSP Wall Clock Timer 0 Compare */
+#define SHIM_DSPWCT1C 0x38 /* DSP Wall Clock Timer 1 Compare */
+
+#define SHIM_DSPWCTCS_T1T (0x1 << 5) /* Timer 1 triggered */
+#define SHIM_DSPWCTCS_T0T (0x1 << 4) /* Timer 0 triggered */
+#define SHIM_DSPWCTCS_T1A (0x1 << 1) /* Timer 1 armed */
+#define SHIM_DSPWCTCS_T0A (0x1 << 0) /* Timer 0 armed */
+
+#define SHIM_CLKCTL 0x78
+#define SHIM_CLKSTS 0x7C
+
+#define SHIM_PWRCTL 0x90
+#define SHIM_PWRSTS 0x92
+#define SHIM_PWRCTL_TCPDSP0PG (0x1 << 0)
+
+/* LP GPDMA Force Dynamic Clock Gating bits, 0--enable */
+#define SHIM_CLKCTL_LPGPDMAFDCGB(x) (0x1 << (26 + x))
+#define SHIM_CLKCTL_TCPLCG(x) (0x1 << (16 + x))
+
+/* Core clock PLL divisor */
+#define SHIM_CLKCTL_DPCS_MASK(x) (0x1 << 2)
+
+/* Prevent Audio PLL Shutdown */
+#define SHIM_CLKCTL_TCPAPLLS (0x1 << 7)
+
+/* 0--from PLL, 1--from oscillator */
+#define SHIM_CLKCTL_HDCS (0x1 << 4)
+
+/* Oscillator select */
+#define SHIM_CLKCTL_HDOCS (0x1 << 2)
+
+/* HP memory clock PLL divisor */
+#define SHIM_CLKCTL_HPMPCS (0x1 << 0)
+
+#define GPDMA_CLKCTL(x) (0x78404 + x*0x100)
+#define GPDMA_FDCGB (0x1 << 0)
+
+#define L2LMCAP 0x71D00
+#define L2MPAT 0x71D04
+
+#define HSPGCTL0 0x71D10
+#define HSRMCTL0 0x71D14
+#define HSPGISTS0 0x71D18
+
+#define HSPGCTL1 0x71D20
+#define HSRMCTL1 0x71D24
+#define HSPGISTS1 0x71D28
+
+#define LSPGCTL 0x71D50
+#define LSRMCTL 0x71D54
+#define LSPGISTS 0x71D58
+
+#define SHIM_L2_MECS (SHIM_BASE + 0xd0)
+
+#define SHIM_LDOCTL 0xA4
+#define SHIM_HPMEM_POWER_ON (0x3 << 0)
+#define SHIM_LPMEM_POWER_BYPASS (0x1 << 0)
+
+#define DSP_INIT_LPGPDMA(x) (0x71A60 + (2*x))
+#define LPGPDMA_CTLOSEL_FLAG (1 << 15)
+#define LPGPDMA_CHOSEL_FLAG (0xFF)
+
+#define DSP_INIT_IOPO 0x71A68
+#define IOPO_DMIC_FLAG (1 << 0)
+#define IOPO_I2S_FLAG (7 << 8)
+
+#define DSP_INIT_GENO 0x71A6C
+#define GENO_MDIVOSEL (1 << 1)
+#define GENO_DIOPTOSEL (1 << 2)
+
+#define DSP_INIT_ALHO 0x71A70
+#define ALHO_ASO_FLAG (1 << 0)
+#define ALHO_CSO_FLAG (1 << 1)
+#define ALHO_CFO_FLAG (1 << 2)
+
+/* host windows */
+#define DMWBA(x) (HOST_WIN_BASE(x) + 0x0)
+#define DMWLO(x) (HOST_WIN_BASE(x) + 0x4)
+
+#define DMWBA_ENABLE (1 << 0)
+#define DMWBA_READONLY (1 << 1)
+
+#ifndef ASSEMBLY
+
+static inline uint16_t shim_read16(uint16_t reg)
+{
+ return *((volatile uint16_t*)(SHIM_BASE + reg));
+}
+
+static inline void shim_write16(uint16_t reg, uint16_t val)
+{
+ *((volatile uint16_t*)(SHIM_BASE + reg)) = val;
+}
+
+static inline uint32_t shim_read(uint32_t reg)
+{
+ return *((volatile uint32_t*)(SHIM_BASE + reg));
+}
+
+static inline void shim_write(uint32_t reg, uint32_t val)
+{
+ *((volatile uint32_t*)(SHIM_BASE + reg)) = val;
+}
+
+static inline uint64_t shim_read64(uint32_t reg)
+{
+ return *((volatile uint64_t*)(SHIM_BASE + reg));
+}
+
+static inline void shim_write64(uint32_t reg, uint64_t val)
+{
+ *((volatile uint64_t*)(SHIM_BASE + reg)) = val;
+}
+
+static inline uint32_t sw_reg_read(uint32_t reg)
+{
+ return *((volatile uint32_t*)(SRAM_SW_REG_BASE + reg));
+}
+
+static inline void sw_reg_write(uint32_t reg, uint32_t val)
+{
+ *((volatile uint32_t*)(SRAM_SW_REG_BASE + reg)) = val;
+}
+
+static inline uint32_t mn_reg_read(uint32_t reg)
+{
+ return *((volatile uint32_t*)(MN_BASE + reg));
+}
+
+static inline void mn_reg_write(uint32_t reg, uint32_t val)
+{
+ *((volatile uint32_t*)(MN_BASE + reg)) = val;
+}
+
+static inline uint32_t irq_read(uint32_t reg)
+{
+ return *((volatile uint32_t*)(IRQ_BASE + reg));
+}
+
+static inline void irq_write(uint32_t reg, uint32_t val)
+{
+ *((volatile uint32_t*)(IRQ_BASE + reg)) = val;
+}
+
+static inline uint32_t ipc_read(uint32_t reg)
+{
+ return *((volatile uint32_t*)(IPC_HOST_BASE + reg));
+}
+
+static inline void ipc_write(uint32_t reg, uint32_t val)
+{
+ *((volatile uint32_t*)(IPC_HOST_BASE + reg)) = val;
+}
+#endif
+
+#endif
diff --git a/src/platform/cannonlake/include/platform/timer.h b/src/platform/cannonlake/include/platform/timer.h
new file mode 100644
index 0000000..e00746d
--- /dev/null
+++ b/src/platform/cannonlake/include/platform/timer.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2017, Intel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the Intel Corporation nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Liam Girdwood <liam.r.girdwood at linux.intel.com>
+ * Keyon Jie <yang.jie at linux.intel.com>
+ * Rander Wang <rander.wang at intel.com>
+ */
+
+#ifndef __PLATFORM_TIMER_H__
+#define __PLATFORM_TIMER_H__
+
+#include <stdint.h>
+#include <reef/timer.h>
+#include <platform/interrupt.h>
+
+#define TIMER_COUNT 5
+
+/* timer numbers must use associated IRQ number */
+#define TIMER0 IRQ_NUM_TIMER1
+#define TIMER1 IRQ_NUM_TIMER2
+#define TIMER2 IRQ_NUM_TIMER3
+#define TIMER3 IRQ_EXT_TSTAMP0_LVL2(0)
+#define TIMER4 IRQ_EXT_TSTAMP1_LVL2(0)
+
+#define TIMER_AUDIO TIMER3
+
+struct comp_dev;
+struct sof_ipc_stream_posn;
+
+int platform_timer_set(struct timer *timer, uint64_t ticks);
+void platform_timer_clear(struct timer *timer);
+uint64_t platform_timer_get(struct timer *timer);
+void platform_timer_start(struct timer *timer);
+void platform_timer_stop(struct timer *timer);
+int platform_timer_register(struct timer *timer,
+ void (*handler)(void *arg), void *arg);
+
+/* get timestamp for host stream DMA position */
+void platform_host_timestamp(struct comp_dev *host,
+ struct sof_ipc_stream_posn *posn);
+
+/* get timestamp for DAI stream DMA position */
+void platform_dai_timestamp(struct comp_dev *dai,
+ struct sof_ipc_stream_posn *posn);
+
+/* get current wallclock for componnent */
+void platform_dai_wallclock(struct comp_dev *dai, uint64_t *wallclock);
+#endif
--
2.14.1
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