[Sound-open-firmware] [PATCH] platform: hsw: Add platform headers for haswell and broadwell
Liam Girdwood
liam.r.girdwood at linux.intel.com
Mon Jan 22 12:33:23 CET 2018
Add SOF platform headers for Haswell and Broadwell
Signed-off-by: Liam Girdwood <liam.r.girdwood at linux.intel.com>
---
src/platform/haswell/include/Makefile.am | 1 +
src/platform/haswell/include/platform/Makefile.am | 10 ++
src/platform/haswell/include/platform/clk.h | 42 ++++++
src/platform/haswell/include/platform/dma.h | 56 ++++++++
src/platform/haswell/include/platform/interrupt.h | 83 ++++++++++++
src/platform/haswell/include/platform/mailbox.h | 76 +++++++++++
src/platform/haswell/include/platform/memory.h | 148 ++++++++++++++++++++++
src/platform/haswell/include/platform/platform.h | 114 +++++++++++++++++
src/platform/haswell/include/platform/shim.h | 129 +++++++++++++++++++
src/platform/haswell/include/platform/timer.h | 70 ++++++++++
10 files changed, 729 insertions(+)
create mode 100644 src/platform/haswell/include/Makefile.am
create mode 100644 src/platform/haswell/include/platform/Makefile.am
create mode 100644 src/platform/haswell/include/platform/clk.h
create mode 100644 src/platform/haswell/include/platform/dma.h
create mode 100644 src/platform/haswell/include/platform/interrupt.h
create mode 100644 src/platform/haswell/include/platform/mailbox.h
create mode 100644 src/platform/haswell/include/platform/memory.h
create mode 100644 src/platform/haswell/include/platform/platform.h
create mode 100644 src/platform/haswell/include/platform/shim.h
create mode 100644 src/platform/haswell/include/platform/timer.h
diff --git a/src/platform/haswell/include/Makefile.am b/src/platform/haswell/include/Makefile.am
new file mode 100644
index 0000000..19f40eb
--- /dev/null
+++ b/src/platform/haswell/include/Makefile.am
@@ -0,0 +1 @@
+SUBDIRS = platform xtensa
diff --git a/src/platform/haswell/include/platform/Makefile.am b/src/platform/haswell/include/platform/Makefile.am
new file mode 100644
index 0000000..8308e14
--- /dev/null
+++ b/src/platform/haswell/include/platform/Makefile.am
@@ -0,0 +1,10 @@
+noinst_HEADERS = \
+ clk.h \
+ dma.h \
+ interrupt.h \
+ mailbox.h \
+ memory.h \
+ platform.h \
+ shim.h \
+ timer.h
+
diff --git a/src/platform/haswell/include/platform/clk.h b/src/platform/haswell/include/platform/clk.h
new file mode 100644
index 0000000..010396d
--- /dev/null
+++ b/src/platform/haswell/include/platform/clk.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2016, Intel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the Intel Corporation nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Liam Girdwood <liam.r.girdwood at linux.intel.com>
+ */
+
+#ifndef __PLATFORM_CLOCK__
+#define __PLATFORM_CLOCK__
+
+#define CLK_CPU 0
+#define CLK_SSP 1
+
+#define CLK_DEFAULT_CPU_HZ 320000000
+#define CLK_MAX_CPU_HZ 320000000
+
+void init_platform_clocks(void);
+
+#endif
diff --git a/src/platform/haswell/include/platform/dma.h b/src/platform/haswell/include/platform/dma.h
new file mode 100644
index 0000000..4780f92
--- /dev/null
+++ b/src/platform/haswell/include/platform/dma.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2016, Intel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the Intel Corporation nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Liam Girdwood <liam.r.girdwood at linux.intel.com>
+ */
+
+#ifndef __PLATFORM_DMA_H__
+#define __PLATFORM_DMA_H__
+
+#include <stdint.h>
+
+#define DMA_ID_DMAC0 0
+#define DMA_ID_DMAC1 1
+
+#define DMA_HANDSHAKE_SSP1_RX 0
+#define DMA_HANDSHAKE_SSP1_TX 1
+#define DMA_HANDSHAKE_SSP0_RX 2
+#define DMA_HANDSHAKE_SSP0_TX 3
+#define DMA_HANDSHAKE_OBFF_0 4
+#define DMA_HANDSHAKE_OBFF_1 5
+#define DMA_HANDSHAKE_OBFF_2 6
+#define DMA_HANDSHAKE_OBFF_3 7
+#define DMA_HANDSHAKE_OBFF_4 8
+#define DMA_HANDSHAKE_OBFF_5 9
+#define DMA_HANDSHAKE_OBFF_6 10
+#define DMA_HANDSHAKE_OBFF_7 11
+#define DMA_HANDSHAKE_OBFF_8 12
+#define DMA_HANDSHAKE_OBFF_9 13
+#define DMA_HANDSHAKE_OBFF_10 14
+#define DMA_HANDSHAKE_OBFF_11 15
+
+#endif
diff --git a/src/platform/haswell/include/platform/interrupt.h b/src/platform/haswell/include/platform/interrupt.h
new file mode 100644
index 0000000..bc5aeab
--- /dev/null
+++ b/src/platform/haswell/include/platform/interrupt.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2016, Intel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the Intel Corporation nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Liam Girdwood <liam.r.girdwood at linux.intel.com>
+ */
+
+#ifndef __INCLUDE_PLATFORM_INTERRUPT__
+#define __INCLUDE_PLATFORM_INTERRUPT__
+
+#include <stdint.h>
+#include <stddef.h>
+#include <reef/interrupt-map.h>
+
+#define PLATFORM_IRQ_CHILDREN 0
+
+/* IRQ numbers */
+#define IRQ_NUM_EXT_SSP0 0 /* Level 1 */
+#define IRQ_NUM_EXT_SSP1 1 /* Level 1 */
+#define IRQ_NUM_EXT_OBFF 2 /* Level 1 */
+#define IRQ_NUM_EXT_IA 4 /* Level 1 */
+#define IRQ_NUM_TIMER1 6 /* Level 1 */
+#define IRQ_NUM_SOFTWARE1 7 /* Level 1 */
+#define IRQ_NUM_EXT_DMAC0 8 /* Level 2 */
+#define IRQ_NUM_EXT_DMAC1 9 /* Level 3 */
+#define IRQ_NUM_TIMER2 10 /* Level 3 */
+#define IRQ_NUM_SOFTWARE2 11 /* Level 3 */
+#define IRQ_NUM_EXT_PARITY 12 /* Level 4 */
+#define IRQ_NUM_TIMER3 13 /* Level 5 */
+#define IRQ_NUM_NMI 14 /* Level 7 */
+
+/* IRQ Masks */
+#define IRQ_MASK_EXT_SSP0 (1 << IRQ_NUM_EXT_SSP0)
+#define IRQ_MASK_EXT_SSP1 (1 << IRQ_NUM_EXT_SSP1)
+#define IRQ_MASK_EXT_OBFF (1 << IRQ_NUM_EXT_OBFF)
+#define IRQ_MASK_EXT_IA (1 << IRQ_NUM_EXT_IA)
+#define IRQ_MASK_TIMER1 (1 << IRQ_NUM_TIMER1)
+#define IRQ_MASK_SOFTWARE1 (1 << IRQ_NUM_SOFTWARE1)
+#define IRQ_MASK_EXT_DMAC0 (1 << IRQ_NUM_EXT_DMAC0)
+#define IRQ_MASK_EXT_DMAC1 (1 << IRQ_NUM_EXT_DMAC1)
+#define IRQ_MASK_TIMER2 (1 << IRQ_NUM_TIMER2)
+#define IRQ_MASK_SOFTWARE2 (1 << IRQ_NUM_SOFTWARE2)
+#define IRQ_MASK_EXT_PARITY (1 << IRQ_NUM_EXT_PARITY)
+#define IRQ_MASK_TIMER2 (1 << IRQ_NUM_TIMER2)
+
+static inline void platform_interrupt_init(void) {}
+
+/* haswell does not support child IRQs */
+static inline struct irq_parent *platform_irq_get_parent(uint32_t irq)
+{
+ return NULL;
+}
+
+void platform_interrupt_set(int irq);
+void platform_interrupt_clear(uint32_t irq, uint32_t mask);
+uint32_t platform_interrupt_get_enabled(void);
+void platform_interrupt_mask(uint32_t irq, uint32_t mask);
+void platform_interrupt_unmask(uint32_t irq, uint32_t mask);
+
+#endif
diff --git a/src/platform/haswell/include/platform/mailbox.h b/src/platform/haswell/include/platform/mailbox.h
new file mode 100644
index 0000000..858eb87
--- /dev/null
+++ b/src/platform/haswell/include/platform/mailbox.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2016, Intel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the Intel Corporation nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Liam Girdwood <liam.r.girdwood at linux.intel.com>
+ */
+
+#ifndef __INCLUDE_PLATFORM_MAILBOX__
+#define __INCLUDE_PLATFORM_MAILBOX__
+
+#include <platform/memory.h>
+
+#if CONFIG_BROADWELL
+#define MAILBOX_HOST_OFFSET 0x0009E000
+#else
+#define MAILBOX_HOST_OFFSET 0x0007E000
+#endif
+
+#define MAILBOX_DSPBOX_OFFSET 0x0
+#define MAILBOX_DSPBOX_SIZE 0x400
+#define MAILBOX_DSPBOX_BASE \
+ (MAILBOX_BASE + MAILBOX_DSPBOX_OFFSET)
+
+#define MAILBOX_HOSTBOX_OFFSET MAILBOX_DSPBOX_SIZE
+#define MAILBOX_HOSTBOX_SIZE 0x400
+#define MAILBOX_HOSTBOX_BASE \
+ (MAILBOX_BASE + MAILBOX_HOSTBOX_OFFSET)
+
+#define MAILBOX_EXCEPTION_OFFSET \
+ (MAILBOX_HOSTBOX_SIZE + MAILBOX_DSPBOX_SIZE)
+#define MAILBOX_EXCEPTION_SIZE 0x100
+#define MAILBOX_EXCEPTION_BASE \
+ (MAILBOX_BASE + MAILBOX_EXCEPTION_OFFSET)
+
+#define MAILBOX_DEBUG_OFFSET \
+ (MAILBOX_EXCEPTION_SIZE + MAILBOX_EXCEPTION_OFFSET)
+#define MAILBOX_DEBUG_SIZE 0x100
+#define MAILBOX_DEBUG_BASE \
+ (MAILBOX_BASE + MAILBOX_DEBUG_OFFSET)
+
+#define MAILBOX_STREAM_OFFSET \
+ (MAILBOX_DEBUG_SIZE + MAILBOX_DEBUG_OFFSET)
+#define MAILBOX_STREAM_SIZE 0x200
+#define MAILBOX_STREAM_BASE \
+ (MAILBOX_BASE + MAILBOX_STREAM_OFFSET)
+
+#define MAILBOX_TRACE_OFFSET \
+ (MAILBOX_STREAM_SIZE + MAILBOX_STREAM_OFFSET)
+#define MAILBOX_TRACE_SIZE 0x380
+#define MAILBOX_TRACE_BASE \
+ (MAILBOX_BASE + MAILBOX_TRACE_OFFSET)
+
+#endif
diff --git a/src/platform/haswell/include/platform/memory.h b/src/platform/haswell/include/platform/memory.h
new file mode 100644
index 0000000..8cbc408
--- /dev/null
+++ b/src/platform/haswell/include/platform/memory.h
@@ -0,0 +1,148 @@
+/*
+ * Copyright (c) 2016, Intel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the Intel Corporation nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Liam Girdwood <liam.r.girdwood at linux.intel.com>
+ */
+
+#ifndef __PLATFORM_MEMORY_H__
+#define __PLATFORM_MEMORY_H__
+
+#include <config.h>
+
+/* physical DSP addresses */
+
+
+#define SHIM_SIZE 0x00001000
+
+#define IRAM_BASE 0x00000000
+#define IRAM_SIZE 0x00050000
+
+#define DRAM0_BASE 0x00400000
+#define DRAM0_VBASE 0x00400000
+
+#define MAILBOX_SIZE 0x00001000
+#define DMA0_SIZE 0x00001000
+#define DMA1_SIZE 0x00001000
+#define SSP0_SIZE 0x00001000
+#define SSP1_SIZE 0x00001000
+
+#if CONFIG_BROADWELL
+#define DRAM0_SIZE 0x000A0000
+#define SHIM_BASE 0xFFFFB000
+#define MAILBOX_BASE 0x0049E000
+#define DMA0_BASE 0xFFFFE000
+#define DMA1_BASE 0xFFFFF000
+#define SSP0_BASE 0xFFFFC000
+#define SSP1_BASE 0xFFFFD000
+
+#else /* HASWELL */
+#define DRAM0_SIZE 0x00080000
+#define SHIM_BASE 0xFFFE7000
+#define MAILBOX_BASE 0x0047E000
+#define DMA0_BASE 0xFFFF0000
+#define DMA1_BASE 0xFFFF8000
+#define SSP0_BASE 0xFFFE8000
+#define SSP1_BASE 0xFFFE9000
+
+#endif
+
+/*
+ * The Heap and Stack on Haswell/Broadwell are organised like this :-
+ *
+ * +--------------------------------------------------------------------------+
+ * | Offset | Region | Size |
+ * +---------------------+----------------+-----------------------------------+
+ * | DRAM0_BASE | RO Data | REEF_DATA_SIZE |
+ * | | Data | |
+ * | | BSS | |
+ * +---------------------+----------------+-----------------------------------+
+ * | HEAP_SYSTEM_BASE | System Heap | HEAP_SYSTEM_SIZE |
+ * +---------------------+----------------+-----------------------------------+
+ * | HEAP_RUNTIME_BASE | Runtime Heap | HEAP_RUNTIME_SIZE |
+ * +---------------------+----------------+-----------------------------------+
+ * | HEAP_BUFFER_BASE | Module Buffers | HEAP_BUFFER_SIZE |
+ * +---------------------+----------------+-----------------------------------+
+ * | REEF_STACK_END | Stack | REEF_STACK_SIZE |
+ * +---------------------+----------------+-----------------------------------+
+ * | REEF_STACK_BASE | | |
+ * +---------------------+----------------+-----------------------------------+
+ */
+
+
+/* Heap section sizes for module pool */
+#define HEAP_RT_COUNT8 0
+#define HEAP_RT_COUNT16 256
+#define HEAP_RT_COUNT32 128
+#define HEAP_RT_COUNT64 64
+#define HEAP_RT_COUNT128 32
+#define HEAP_RT_COUNT256 16
+#define HEAP_RT_COUNT512 8
+#define HEAP_RT_COUNT1024 4
+
+/* Heap configuration */
+#define REEF_DATA_SIZE 0xa000
+
+#define HEAP_SYSTEM_BASE (DRAM0_BASE + REEF_DATA_SIZE)
+#define HEAP_SYSTEM_SIZE 0x2000
+
+#define HEAP_RUNTIME_BASE (HEAP_SYSTEM_BASE + HEAP_SYSTEM_SIZE)
+#define HEAP_RUNTIME_SIZE \
+ (HEAP_RT_COUNT8 * 8 + HEAP_RT_COUNT16 * 16 + \
+ HEAP_RT_COUNT32 * 32 + HEAP_RT_COUNT64 * 64 + \
+ HEAP_RT_COUNT128 * 128 + HEAP_RT_COUNT256 * 256 + \
+ HEAP_RT_COUNT512 * 512 + HEAP_RT_COUNT1024 * 1024)
+
+#define HEAP_BUFFER_BASE (HEAP_RUNTIME_BASE + HEAP_RUNTIME_SIZE)
+#define HEAP_BUFFER_SIZE \
+ (DRAM0_SIZE - HEAP_RUNTIME_SIZE - REEF_STACK_SIZE - HEAP_SYSTEM_SIZE)
+
+#define HEAP_BUFFER_BLOCK_SIZE 0x180
+#define HEAP_BUFFER_COUNT (HEAP_BUFFER_SIZE / HEAP_BUFFER_BLOCK_SIZE)
+
+/* DMA buffer heap is the same physical memory as buffer heap on baytrail */
+#define HEAP_DMA_BUFFER_BASE 0
+#define HEAP_DMA_BUFFER_SIZE 0
+#define HEAP_DMA_BUFFER_BLOCK_SIZE 0
+#define HEAP_DMA_BUFFER_COUNT 0
+
+/* Stack configuration */
+#define REEF_STACK_SIZE 0x1000
+#define REEF_STACK_BASE (DRAM0_BASE + DRAM0_SIZE)
+#define REEF_STACK_END (REEF_STACK_BASE - REEF_STACK_SIZE)
+
+/* Vector and literal sizes - not in core-isa.h */
+#define REEF_MEM_VECT_LIT_SIZE 0x4
+#define REEF_MEM_VECT_TEXT_SIZE 0x1c
+#define REEF_MEM_VECT_SIZE (REEF_MEM_VECT_TEXT_SIZE + REEF_MEM_VECT_LIT_SIZE)
+
+#define REEF_MEM_RESET_TEXT_SIZE 0x2e0
+#define REEF_MEM_RESET_LIT_SIZE 0x120
+#define REEF_MEM_VECBASE_LIT_SIZE 0x178
+
+#define REEF_MEM_RO_SIZE 0x8
+
+#endif
diff --git a/src/platform/haswell/include/platform/platform.h b/src/platform/haswell/include/platform/platform.h
new file mode 100644
index 0000000..8475e31
--- /dev/null
+++ b/src/platform/haswell/include/platform/platform.h
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2016, Intel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the Intel Corporation nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Liam Girdwood <liam.r.girdwood at linux.intel.com>
+ */
+
+#ifndef __PLATFORM_PLATFORM_H__
+#define __PLATFORM_PLATFORM_H__
+
+#include <platform/shim.h>
+#include <platform/interrupt.h>
+#include <uapi/ipc.h>
+
+struct reef;
+
+/* IPC Interrupt */
+#define PLATFORM_IPC_INTERUPT IRQ_NUM_EXT_IA
+
+/* Host page size */
+#define HOST_PAGE_SIZE 4096
+#define PLATFORM_PAGE_TABLE_SIZE 256
+
+/* pipeline IRQ */
+#define PLATFORM_SCHEDULE_IRQ IRQ_NUM_SOFTWARE2
+
+#define PLATFORM_IRQ_TASK_HIGH IRQ_NUM_SOFTWARE2
+#define PLATFORM_IRQ_TASK_MED IRQ_NUM_SOFTWARE1
+#define PLATFORM_IRQ_TASK_LOW IRQ_NUM_SOFTWARE1
+
+#define PLATFORM_SCHEDULE_COST 200
+
+/* maximum preload pipeline depth */
+#define MAX_PRELOAD_SIZE 20
+
+/* DMA treats PHY addresses as host address unless within DSP region */
+#define PLATFORM_HOST_DMA_MASK 0xFFF00000
+
+/* Platform stream capabilities */
+#define PLATFORM_MAX_CHANNELS 4
+#define PLATFORM_MAX_STREAMS 5
+
+/* clock source used by scheduler for deadline calculations */
+#define PLATFORM_SCHED_CLOCK CLK_SSP
+
+/* DMA channel drain timeout in microseconds - TODO: caclulate based on topology */
+#define PLATFORM_DMA_TIMEOUT 1333
+
+/* DMA host transfer timeouts in microseconds */
+#define PLATFORM_HOST_DMA_TIMEOUT 50
+
+/* WorkQ window size in microseconds */
+#define PLATFORM_WORKQ_WINDOW 2000
+
+/* platform WorkQ clock */
+#define PLATFORM_WORKQ_CLOCK CLK_SSP
+
+/* local buffer size of DMA tracing */
+#define DMA_TRACE_LOCAL_SIZE HOST_PAGE_SIZE
+
+/* the interval of DMA trace copying */
+#define DMA_TRACE_PERIOD 500000
+
+/*
+ * the interval of reschedule DMA trace copying in special case like half
+ * fullness of local DMA trace buffer
+ */
+#define DMA_TRACE_RESCHEDULE_TIME 5000
+
+/* DMAC used for trace DMA */
+#define PLATFORM_TRACE_DMAC DMA_ID_DMAC0
+
+/* DSP should be idle in this time frame */
+#define PLATFORM_IDLE_TIME 750000
+
+/* Platform defined panic code */
+#define platform_panic(__x) \
+ shim_write(SHIM_IPCD, (0xdead000 | __x) & 0x3fffffff)
+
+/* Platform defined trace code */
+#define platform_trace_point(__x) \
+ shim_write(SHIM_IPCD, ((__x) & 0x3fffffff))
+/*
+ * APIs declared here are defined for every platform and IPC mechanism.
+ */
+
+int platform_boot_complete(uint32_t boot_message);
+
+int platform_init(struct reef *reef);
+
+#endif
diff --git a/src/platform/haswell/include/platform/shim.h b/src/platform/haswell/include/platform/shim.h
new file mode 100644
index 0000000..ecbe665
--- /dev/null
+++ b/src/platform/haswell/include/platform/shim.h
@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) 2016, Intel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the Intel Corporation nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Liam Girdwood <liam.r.girdwood at linux.intel.com>
+ */
+
+#ifndef __PLATFORM_SHIM_H__
+#define __PLATFORM_SHIM_H__
+
+#include <platform/memory.h>
+#include <stdint.h>
+
+#define SHIM_CSR 0x00
+#define SHIM_ISRX 0x18
+#define SHIM_ISRD 0x20
+#define SHIM_IMRX 0x28
+#define SHIM_IMRD 0x30
+#define SHIM_IPCX 0x38 /* IPC IA -> SST */
+#define SHIM_IPCD 0x40 /* IPC SST -> IA */
+
+#define SHIM_CLKCTL 0x78
+
+#define SHIM_CSR2 0x80
+#define SHIM_LTRC 0xE0
+#define SHIM_HMDC 0xE8
+
+#define SHIM_SHIM_BEGIN SHIM_CSR
+#define SHIM_SHIM_END SHIM_HMDC
+
+/* CSR 0x0 */
+#define SHIM_CSR_RST (0x1 << 1)
+#define SHIM_CSR_STALL (0x1 << 10)
+#define SHIM_CSR_SDPM0 (0x1 << 11)
+#define SHIM_CSR_SDPM1 (0x1 << 12)
+#define SHIM_CSR_SFCR0 (0x1 << 27)
+#define SHIM_CSR_SFCR1 (0x1 << 28)
+#define SHIM_CSR_DCS(x) (x << 4)
+#define SHIM_CSR_DCS_MASK (0x7 << 4)
+
+/* ISRX 0x18 */
+#define SHIM_ISRX_BUSY (0x1 << 1)
+#define SHIM_ISRX_DONE (0x1 << 0)
+
+/* ISRD / ISD */
+#define SHIM_ISRD_BUSY (0x1 << 1)
+#define SHIM_ISRD_DONE (0x1 << 0)
+
+/* IMRX / IMC */
+#define SHIM_IMRX_BUSY (0x1 << 1)
+#define SHIM_IMRX_DONE (0x1 << 0)
+
+/* IMRD / IMD */
+#define SHIM_IMRD_DONE (0x1 << 0)
+#define SHIM_IMRD_BUSY (0x1 << 1)
+#define SHIM_IMRD_SSP0 (0x1 << 16)
+#define SHIM_IMRD_SSP1 (0x1 << 17)
+#define SHIM_IMRD_DMAC0 (0x1 << 21)
+#define SHIM_IMRD_DMAC1 (0x1 << 22)
+#define SHIM_IMRD_DMAC (SHIM_IMRD_DMAC0 | SHIM_IMRD_DMAC1)
+
+/* IPCX / IPCCH */
+#define SHIM_IPCX_DONE (0x1 << 30)
+#define SHIM_IPCX_BUSY (0x1 << 31)
+
+/* IPCDH */
+#define SHIM_IPCD_DONE (0x1 << 30)
+#define SHIM_IPCD_BUSY (0x1 << 31)
+
+/* CLKCTL */
+#define SHIM_CLKCTL_SMOS(x) (x << 24)
+#define SHIM_CLKCTL_MASK (3 << 24)
+#define SHIM_CLKCTL_DCPLCG (1 << 18)
+#define SHIM_CLKCTL_SSP1_EN (1 << 17)
+#define SHIM_CLKCTL_SSP0_EN (1 << 16)
+
+/* CSR2 / CS2 */
+#define SHIM_CSR2_SDFD_SSP0 (1 << 1)
+#define SHIM_CSR2_SDFD_SSP1 (1 << 2)
+
+/* LTRC */
+#define SHIM_LTRC_VAL(x) (x << 0)
+
+/* HMDC */
+#define SHIM_HMDC_HDDA0(x) (x << 0)
+#define SHIM_HMDC_HDDA1(x) (x << 8)
+#define SHIM_HMDC_HDDA_CH_MASK 0xFF
+#define SHIM_HMDC_HDDA_E0_ALLCH SHIM_HMDC_HDDA0(SHIM_HMDC_HDDA_CH_MASK)
+#define SHIM_HMDC_HDDA_E1_ALLCH SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_CH_MASK)
+#define SHIM_HMDC_HDDA_ALLCH (SHIM_HMDC_HDDA_E0_ALLCH | SHIM_HMDC_HDDA_E1_ALLCH)
+
+/* PMCS */
+#define PCI_PMCS 0x84
+#define PCI_PMCS_PS_MASK 0x3
+
+static inline uint32_t shim_read(uint32_t reg)
+{
+ return *((volatile uint32_t*)(SHIM_BASE + reg));
+}
+
+static inline void shim_write(uint32_t reg, uint32_t val)
+{
+ *((volatile uint32_t*)(SHIM_BASE + reg)) = val;
+}
+
+#endif
diff --git a/src/platform/haswell/include/platform/timer.h b/src/platform/haswell/include/platform/timer.h
new file mode 100644
index 0000000..0aa3ed2
--- /dev/null
+++ b/src/platform/haswell/include/platform/timer.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2016, Intel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the Intel Corporation nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Liam Girdwood <liam.r.girdwood at linux.intel.com>
+ */
+
+
+#ifndef __PLATFORM_TIMER_H__
+#define __PLATFORM_TIMER_H__
+
+#include <stdint.h>
+#include <reef/timer.h>
+#include <platform/interrupt.h>
+
+#define TIMER_COUNT 3
+
+/* timer numbers must use associated IRQ number */
+#define TIMER0 IRQ_NUM_TIMER1
+#define TIMER1 IRQ_NUM_TIMER2
+#define TIMER2 IRQ_NUM_TIMER3
+
+#define TIMER_AUDIO TIMER0
+
+struct comp_dev;
+struct sof_ipc_stream_posn;
+
+extern struct timer *platform_timer;
+
+int platform_timer_set(struct timer *timer, uint64_t ticks);
+void platform_timer_clear(struct timer *timer);
+uint64_t platform_timer_get(struct timer *timer);
+void platform_timer_start(struct timer *timer);
+void platform_timer_stop(struct timer *timer);
+
+/* get timestamp for host stream DMA position */
+void platform_host_timestamp(struct comp_dev *host,
+ struct sof_ipc_stream_posn *posn);
+
+/* get timestamp for DAI stream DMA position */
+void platform_dai_timestamp(struct comp_dev *dai,
+ struct sof_ipc_stream_posn *posn);
+
+/* get current wallclock for componnent */
+void platform_dai_wallclock(struct comp_dev *dai, uint64_t *wallclock);
+
+#endif
--
2.14.1
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