[Sound-open-firmware] [PATCH 3/5] SRC: Increase default DSP clock speed in BYT platform

[Seppo Ingalsuo]

As temporary fix to allow SRC to run do not drop clock frequency to
minimum after BYT platform boot is completed.

Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo at linux.intel.com>
---
 src/platform/baytrail/platform.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/platform/baytrail/platform.c b/src/platform/baytrail/platform.c
index b8c3e49..0979af8 100644
--- a/src/platform/baytrail/platform.c
+++ b/src/platform/baytrail/platform.c
@@ -94,7 +94,10 @@ int platform_boot_complete(uint32_t boot_message)
 	shim_write(SHIM_IPCDH, SHIM_IPCDH_BUSY);
 
 	/* boot now complete so we can relax the CPU */
-	clock_set_freq(CLK_CPU, CLK_DEFAULT_CPU_HZ);
+	/* For now skip this to gain more processing performance
+	 * for SRC component.
+	 */
+	/* clock_set_freq(CLK_CPU, CLK_DEFAULT_CPU_HZ); */
 
 	return 0;
 }
-- 
2.11.0