[Sound-open-firmware] [PATCH 7/8] ssp: change stream format to S24_4LE

[Keyon Jie]

1. stream format changed to S24_LE;
2. ssp device period size changed to 512 Byte;
3. dai config frame size(24b), bclks_fs(50), mclks_fs(400);

it is verified work fine on minnow max + rt5651, for both
SSP_CLK_EXT and SSP_CLK_AUDIO clock mode.

Signed-off-by: Keyon Jie <yang.jie at linux.intel.com>
---
 src/ipc/intel-ipc.c                               | 7 ++++---
 src/platform/baytrail/include/platform/platform.h | 4 ++--
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/src/ipc/intel-ipc.c b/src/ipc/intel-ipc.c
index b159980..33727a0 100644
--- a/src/ipc/intel-ipc.c
+++ b/src/ipc/intel-ipc.c
@@ -564,9 +564,10 @@ static uint32_t ipc_device_set_formats(uint32_t header)
 	dai_dev->dai_config.mclk = config_req.clock_frequency;
 	dai_dev->dai_config.format = DAI_FMT_I2S | DAI_FMT_CONT |
 		DAI_FMT_NB_NF | DAI_FMT_CBS_CFS;
-	dai_dev->dai_config.frame_size = 32;	/* TODO 16bit stereo hard coded */
-	dai_dev->dai_config.bclk_fs = 32;	/* 32 BCLKs per frame - */
-	dai_dev->dai_config.mclk_fs = 256;	
+	/* TODO: convert from dai stream_format */
+	dai_dev->dai_config.frame_size = 24;
+	dai_dev->dai_config.bclk_fs = 50;	/* 50 BCLKs per frame - */
+	dai_dev->dai_config.mclk_fs = 400;
 	dai_dev->dai_config.clk_src = SSP_CLK_EXT;
 
 	/* set SSP M/N dividers */
diff --git a/src/platform/baytrail/include/platform/platform.h b/src/platform/baytrail/include/platform/platform.h
index b0000b4..3f7be88 100644
--- a/src/platform/baytrail/include/platform/platform.h
+++ b/src/platform/baytrail/include/platform/platform.h
@@ -39,7 +39,7 @@
 #define PLATFORM_SSP_PORT	2
 
 /* default SSP stream format - need aligned with codec setting*/
-#define PLATFORM_SSP_STREAM_FORMAT	STREAM_FORMAT_S16_LE
+#define PLATFORM_SSP_STREAM_FORMAT	STREAM_FORMAT_S24_4LE
 
 /* IPC Interrupt */
 #define PLATFORM_IPC_INTERUPT	IRQ_NUM_EXT_IA
@@ -62,7 +62,7 @@
 #define PLAT_HOST_PERIODS	2	/* give enough latency for DMA refill */
 
 /* Platform Dev DMA buffer config - these should align with DMA engine */
-#define PLAT_DEV_PERSIZE	256	/* must be multiple of DMA+DEV burst size */
+#define PLAT_DEV_PERSIZE	512	/* must be multiple of DMA+DEV burst size */
 #define PLAT_DEV_PERIODS	2	/* give enough latency for DMA refill */
 
 /* DMA channel drain timeout in microseconds */
-- 
2.7.4