[PATCH v7 2/2] dt-bindings: soundwire: qcom: Add bindings for audio clock reset control property

[Srinivasa Rao Mandadapu]

Update description for audio clock reset control property, which is required
for latest chipsets, to allow rx, tx and wsa bus clock enabling in software
 control mode by configuring dynamic clock gating control registers.

Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam at quicinc.com>
Co-developed-by: Venkata Prasad Potturu <quic_potturu at quicinc.com>
Signed-off-by: Venkata Prasad Potturu <quic_potturu at quicinc.com>
---
 Documentation/devicetree/bindings/soundwire/qcom,sdw.txt | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt b/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt
index b93a2b3..32e156d 100644
--- a/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt
+++ b/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt
@@ -150,6 +150,18 @@ board specific bus parameters.
 		    or applicable for the respective data port.
 		    More info in MIPI Alliance SoundWire 1.0 Specifications.
 
+- reset:
+	Usage: optional
+	Value type: <prop-encoded-array>
+	Definition: Should specify the SoundWire audio CSR reset controller interface,
+		    which is required for SoundWire version 1.6.0 and above.
+
+- reset-names:
+	Usage: optional
+	Value type: <stringlist>
+	Definition: should be "swr_audio_cgcr" for SoundWire audio CSR reset
+		    controller interface.
+
 Note:
 	More Information on detail of encoding of these fields can be
 found in MIPI Alliance SoundWire 1.0 Specifications.
@@ -168,6 +180,8 @@ soundwire: soundwire at c85 {
 	interrupts = <20 IRQ_TYPE_EDGE_RISING>;
 	clocks = <&wcc>;
 	clock-names = "iface";
+	resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>;
+	reset-names = "swr_audio_cgcr";
 	#sound-dai-cells = <1>;
 	qcom,dports-type = <0>;
 	qcom,dout-ports	= <6>;
-- 
2.7.4