[PATCH v8 4/8] dt-bindings: mediatek: mt8186: add audio afe document
Jiaxin Yu
jiaxin.yu at mediatek.com
Sat Jun 25 21:08:48 CEST 2022
Add mt8186 audio afe document.
Signed-off-by: Jiaxin Yu <jiaxin.yu at mediatek.com>
Reviewed-by: Rob Herring <robh at kernel.org>
---
.../bindings/sound/mt8186-afe-pcm.yaml | 175 ++++++++++++++++++
1 file changed, 175 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/mt8186-afe-pcm.yaml
diff --git a/Documentation/devicetree/bindings/sound/mt8186-afe-pcm.yaml b/Documentation/devicetree/bindings/sound/mt8186-afe-pcm.yaml
new file mode 100644
index 000000000000..88f82d096443
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/mt8186-afe-pcm.yaml
@@ -0,0 +1,175 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/mt8186-afe-pcm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek AFE PCM controller for mt8186
+
+maintainers:
+ - Jiaxin Yu <jiaxin.yu at mediatek.com>
+
+properties:
+ compatible:
+ const: mediatek,mt8186-sound
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ const: audiosys
+
+ mediatek,apmixedsys:
+ $ref: "/schemas/types.yaml#/definitions/phandle"
+ description: The phandle of the mediatek apmixedsys controller
+
+ mediatek,infracfg:
+ $ref: "/schemas/types.yaml#/definitions/phandle"
+ description: The phandle of the mediatek infracfg controller
+
+ mediatek,topckgen:
+ $ref: "/schemas/types.yaml#/definitions/phandle"
+ description: The phandle of the mediatek topckgen controller
+
+ clocks:
+ items:
+ - description: audio infra sys clock
+ - description: audio infra 26M clock
+ - description: audio top mux
+ - description: audio intbus mux
+ - description: mainpll 136.5M clock
+ - description: faud1 mux
+ - description: apll1 clock
+ - description: faud2 mux
+ - description: apll2 clock
+ - description: audio engen1 mux
+ - description: apll1_d8 22.5792M clock
+ - description: audio engen2 mux
+ - description: apll2_d8 24.576M clock
+ - description: i2s0 mclk mux
+ - description: i2s1 mclk mux
+ - description: i2s2 mclk mux
+ - description: i2s4 mclk mux
+ - description: tdm mclk mux
+ - description: i2s0_mck divider
+ - description: i2s1_mck divider
+ - description: i2s2_mck divider
+ - description: i2s4_mck divider
+ - description: tdm_mck divider
+ - description: audio hires mux
+ - description: 26M clock
+
+ clock-names:
+ items:
+ - const: aud_infra_clk
+ - const: mtkaif_26m_clk
+ - const: top_mux_audio
+ - const: top_mux_audio_int
+ - const: top_mainpll_d2_d4
+ - const: top_mux_aud_1
+ - const: top_apll1_ck
+ - const: top_mux_aud_2
+ - const: top_apll2_ck
+ - const: top_mux_aud_eng1
+ - const: top_apll1_d8
+ - const: top_mux_aud_eng2
+ - const: top_apll2_d8
+ - const: top_i2s0_m_sel
+ - const: top_i2s1_m_sel
+ - const: top_i2s2_m_sel
+ - const: top_i2s4_m_sel
+ - const: top_tdm_m_sel
+ - const: top_apll12_div0
+ - const: top_apll12_div1
+ - const: top_apll12_div2
+ - const: top_apll12_div4
+ - const: top_apll12_div_tdm
+ - const: top_mux_audio_h
+ - const: top_clk26m_clk
+
+required:
+ - compatible
+ - interrupts
+ - resets
+ - reset-names
+ - mediatek,apmixedsys
+ - mediatek,infracfg
+ - mediatek,topckgen
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ afe: mt8186-afe-pcm at 11210000 {
+ compatible = "mediatek,mt8186-sound";
+ reg = <0x11210000 0x2000>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&watchdog 17>; //MT8186_TOPRGU_AUDIO_SW_RST
+ reset-names = "audiosys";
+ mediatek,apmixedsys = <&apmixedsys>;
+ mediatek,infracfg = <&infracfg>;
+ mediatek,topckgen = <&topckgen>;
+ clocks = <&infracfg_ao 44>, //CLK_INFRA_AO_AUDIO
+ <&infracfg_ao 54>, //CLK_INFRA_AO_AUDIO_26M_BCLK
+ <&topckgen 15>, //CLK_TOP_AUDIO
+ <&topckgen 16>, //CLK_TOP_AUD_INTBUS
+ <&topckgen 70>, //CLK_TOP_MAINPLL_D2_D4
+ <&topckgen 17>, //CLK_TOP_AUD_1
+ <&apmixedsys 12>, //CLK_APMIXED_APLL1
+ <&topckgen 18>, //CLK_TOP_AUD_2
+ <&apmixedsys 13>, //CLK_APMIXED_APLL2
+ <&topckgen 19>, //CLK_TOP_AUD_ENGEN1
+ <&topckgen 101>, //CLK_TOP_APLL1_D8
+ <&topckgen 20>, //CLK_TOP_AUD_ENGEN2
+ <&topckgen 104>, //CLK_TOP_APLL2_D8
+ <&topckgen 63>, //CLK_TOP_APLL_I2S0_MCK_SEL
+ <&topckgen 64>, //CLK_TOP_APLL_I2S1_MCK_SEL
+ <&topckgen 65>, //CLK_TOP_APLL_I2S2_MCK_SEL
+ <&topckgen 66>, //CLK_TOP_APLL_I2S4_MCK_SEL
+ <&topckgen 67>, //CLK_TOP_APLL_TDMOUT_MCK_SEL
+ <&topckgen 131>, //CLK_TOP_APLL12_CK_DIV0
+ <&topckgen 132>, //CLK_TOP_APLL12_CK_DIV1
+ <&topckgen 133>, //CLK_TOP_APLL12_CK_DIV2
+ <&topckgen 134>, //CLK_TOP_APLL12_CK_DIV4
+ <&topckgen 135>, //CLK_TOP_APLL12_CK_DIV_TDMOUT_M
+ <&topckgen 44>, //CLK_TOP_AUDIO_H
+ <&clk26m>;
+ clock-names = "aud_infra_clk",
+ "mtkaif_26m_clk",
+ "top_mux_audio",
+ "top_mux_audio_int",
+ "top_mainpll_d2_d4",
+ "top_mux_aud_1",
+ "top_apll1_ck",
+ "top_mux_aud_2",
+ "top_apll2_ck",
+ "top_mux_aud_eng1",
+ "top_apll1_d8",
+ "top_mux_aud_eng2",
+ "top_apll2_d8",
+ "top_i2s0_m_sel",
+ "top_i2s1_m_sel",
+ "top_i2s2_m_sel",
+ "top_i2s4_m_sel",
+ "top_tdm_m_sel",
+ "top_apll12_div0",
+ "top_apll12_div1",
+ "top_apll12_div2",
+ "top_apll12_div4",
+ "top_apll12_div_tdm",
+ "top_mux_audio_h",
+ "top_clk26m_clk";
+ };
+
+...
--
2.18.0
More information about the Alsa-devel
mailing list