[PATCH 2/5] ASoC: xilinx: xlnx_formatter_pcm: Handle sysclk setting

[Mark Brown]

On Thu, Jan 06, 2022 at 05:38:42PM +0000, Robert Hancock wrote:
> On Thu, 2022-01-06 at 12:26 +0000, Mark Brown wrote:

> > Does the IP actually cope properly with inexact ratios, especially if
> > the actual clock rate is lower than mclk_fs would suggest?  It's more
> > common to be able to tolerate a higher clock than specified.

> Unknown at this point - the test setup I have has a fixed sample rate so I
> can't really test it. The documentation is unclear on exactly why this register
> exists and what it's used for, it just indicates it should be set for the
> sample rate to MCLK multiplier. All I really know for sure is that with it left
> set to the default of 384 when the actual multiplier is 256, it doesn't work
> properly.

Generally the IP will have to do more work than can be done in a single
clock cycle for each bit and needs everything to be done with
synchronous clocks to avoid data corruption.  Based on your report there
it seems like it definitely doesn't tolerate being underclocked well so
DIV_ROUND_CLOSEST is not what's wanted.  Requiring an exact match would
be safest.
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 488 bytes
Desc: not available
URL: <http://mailman.alsa-project.org/pipermail/alsa-devel/attachments/20220106/cf5b05df/attachment.sig>