[PATCH v1 1/3] ASoC: atmel: Remove system clock tree configuration for at91sam9g20ek

[Codrin.Ciubotariu at microchip.com]

On 25.03.2022 17:42, Mark Brown wrote:
> The MCLK of the WM8731 on the AT91SAM9G20-EK board is connected to the
> PCK0 output of the SoC, intended in the reference software to be supplied
> using PLLB and programmed to 12MHz. As originally written for use with a
> board file the audio driver was responsible for configuring the entire tree
> but in the conversion to the common clock framework the registration of
> the named pck0 and pllb clocks was removed so the driver has failed to
> instantiate ever since.
> 
> Since the WM8731 driver has had support for managing a MCLK provided via
> the common clock framework for some time we can simply drop all the clock
> management code from the machine driver other than configuration of the
> sysclk rate, the CODEC driver still respects that configuration from the
> machine driver.
> 
> Fixes: ff78a189b0ae55f ("ARM: at91: remove old at91-specific clock driver")
> Signed-off-by: Mark Brown <broonie at kernel.org>

Reviewed-by: Codrin Ciubotariu <codrin.ciubotariu at microchip.com>

Thank you for addressing this!

Best regards,
Codrin