[RFC PATCH v1 0/1] ASoC: meson: aiu: HDMI codec control questions and issues

[Mark Brown]

On Sun, Oct 03, 2021 at 09:17:39PM +0200, Martin Blumenstingl wrote:

> old 32-bit u-boot sources from the Endless Mini do have some
> documentation on AIU_I2S_SYNC [0]:
> // 8'b0_000_1_1_10
> // A write to this register will cause the interface to repeat the current
> // sample. Can be used to regain synchronization.
> // A read from this register indicates that the next sample to be sent
> // out of the interface should go into the _left_ channel of the dac.

> There's also a note about AIU_I2S_MISC stating:
> // Bit 4 if true, force each audio data to left or right according to
> the bit attached with the audio data
> // This bit should be used with Register AIU_i2s_sync(0x511) together

> To be honest: to me this is not helpful since I don't understand
> how/why the left channel is of importance.

The left channel is important because for most (I think all?) audio
formats the first channel sent after each frame sync is the left
channel, if you're trying to resync it's useful to know when a left
frame is going to be sent.

> 
> > At the time, It was completely new driver. Even if was not rock solid,
> > it was still progress and I opted to upstream it with an imperfect 8ch
> > support so people could help debug it. This was mentioned in the
> > original submission.
> >
> > The other solution is to restrict to 2ch mode and remove
> > AIU_RST_SOFT_I2S_FAST and AIU_I2S_SYNC pokes. There will be no noise
> > anymore.
> I think Christian (Hewitt) agrees on this point as he mentioned that
> your earlier versions of the AIU code (before it got upstream) were
> not affected by the "machine gun noise" issue.
> Does the documentation from above give you any new ideas (assuming
> that it's correct since it's the best we have)? Should I try playing
> with AIU_RST_SOFT_I2S_FAST and AIU_I2S_SYNC to see if I can make a
> difference?
> 
> [...]
> > Here you describe a DAI link (think of it as wires) between the SPDIF
> > encoder (output) and AIU_HDMI input PCM. This is not what the HW is and
> > it is not possible.
> >
> > Let's start from the HDMI controller.
> > The designware (on amlogic SoC) has 2 interface for audio input.
> > 1) PCM/I2S: a classic interface 2 clocks and N data line
> > 2) SPDIF: The Sony Philips 1 wire interface
> The Transwitch HDMI TX controller supports these two inputs so even
> though the IP is different the basic functionality (which we'll
> discuss below) is the same.
> 
> > Whatever comes up on 1) has to be some sort of i2s signal. So SPDIF
> > won't fly there.
> I agree with this
> 
> > AIU_HDMI output is Hardwired to 1). It is just just a digital mux,
> > implemented as an ASoC codec which allows to seleted one of 2 audio
> > sources:
> > A) the i2s output implemented as part of the AIU
> > B) the PCM output, part the AUDIN (yes, an output in AUDIN) block. This
> > is not implemented ATM.
> This is some interesting information, I thought that PCM was used
> because PCM audio can be transmitted over SPDIF.
> 
> For A) my understanding is different though:
> - for AIU_HDMI_CLK_DATA_CTRL[5:4] (HDMI_DATA_SEL) your description
> matches my understanding. For me it makes sense that SPDIF data cannot
> be selected with this register since it's a one-wire protocol (and
> doesn't have separate data/clock lines). Value 0x2 selects the I2S
> data interface
> - for AIU_HDMI_CLK_DATA_CTRL[1:0] (HDMI_DATA_CLK_SEL) however I have a
> different understanding: 0x0 disables the clock signal to the HDMI TX
> controller, 0x1 selects the PCM clock (which now I have learned is
> related to the AUDIN block) and 0x2 selects the "AIU clock" (see
> below)
> - my understanding is that "AIU clock" comes from AIU_CLK_CTRL_MORE[6]
> (HDMITX_SEL_AOCLKX2) where 0x0 selects "cts_i958 as AIU clk to
> hdmi_tx_audio_master_clk" (SPDIF clock) and 0x1 selects
> "cts_aoclkx2_int as AIU clk to hdmi_tx_audio_master_clk" (I2S clock)
> 
> So to me this means that there's three different muxes:
> - data mux to choose between 0x0 (all zeros), 0x1 (PCM) and 0x2 (I2S)
> - clock mux to choose between 0x0 (disabled), 0x1 (PCM) and 0x2
> (hdmi_tx_audio_master_clk)
> - hdmi_tx_audio_master_clk clock mux to choose between 0x0 (cts_i958)
> and 0x1 (cts_aoclkx2_int)
> 
> Based on that I think that it's not possible to have AIU output the
> I2S and SPDIF signals at the same time to the HDMI TX controller and
> then letting the HDMI TX controller choose which one to use.
> Based on whichever signal (I2S or SPDIF) we want to use for HDMI we
> need to configure AIU accordingly (data and clock).
> 
> [...]
> > It is not meant to. The dai_link and the endpoint are i2s.
> > Your HDMI controller should have 2 inputs and should have a way to
> > select one or the other. The format at each of the (internal) input does
> > not change
> ah, that makes sense.
> Let's say AIU has some internal muxing for the HDMI output then AIU
> would have two outputs as well (let's call them HDMI_OUT_I2S and
> HDMI_OUT_SPDIF).
> Then I'd wire up each of these to their corresponding inputs on the
> HDMI TX controller.
> 
> 
> Best regards,
> Martin
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