[RESEND PATCH v6 6/6] arm64: tegra: Audio graph sound card for Jetson Nano and TX1
Sameer Pujar
spujar at nvidia.com
Tue Jan 19 10:28:16 CET 2021
Enable support for audio-graph based sound card on Jetson-Nano and
Jetson-TX1. Depending on the platform, required I/O interfaces are
enabled.
* Jetson-Nano: Enable I2S3, I2S4, DMIC1 and DMIC2.
* Jetson-TX1: Enable all I2S and DMIC interfaces.
Signed-off-by: Sameer Pujar <spujar at nvidia.com>
Reviewed-by: Jon Hunter <jonathanh at nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 262 +++++++++++++++++++++
arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 146 ++++++++++++
2 files changed, 408 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
index 69102dc..747ab93 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
@@ -3,6 +3,7 @@
#include "tegra210-p2180.dtsi"
#include "tegra210-p2597.dtsi"
+#include "tegra210-audio-graph.dtsi"
/ {
model = "NVIDIA Jetson TX1 Developer Kit";
@@ -127,4 +128,265 @@
status = "okay";
};
};
+
+ tegra_sound {
+ status = "okay";
+
+ compatible = "nvidia,tegra210-audio-graph-card";
+
+ dais = /* FE */
+ <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,
+ <&admaif4_port>, <&admaif5_port>, <&admaif6_port>,
+ <&admaif7_port>, <&admaif8_port>, <&admaif9_port>,
+ <&admaif10_port>,
+ /* Router */
+ <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s3_port>,
+ <&xbar_i2s4_port>, <&xbar_i2s5_port>, <&xbar_dmic1_port>,
+ <&xbar_dmic2_port>, <&xbar_dmic3_port>,
+ /* I/O DAP Ports */
+ <&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>,
+ <&i2s5_port>, <&dmic1_port>, <&dmic2_port>, <&dmic3_port>;
+
+ label = "jetson-tx1-ape";
+ };
+};
+
+&tegra_admaif {
+ status = "okay";
+};
+
+&tegra_ahub {
+ status = "okay";
+
+ ports {
+ xbar_i2s1_port: port at a {
+ reg = <0xa>;
+ xbar_i2s1_ep: endpoint {
+ remote-endpoint = <&i2s1_cif_ep>;
+ };
+ };
+ xbar_i2s2_port: port at b {
+ reg = <0xb>;
+ xbar_i2s2_ep: endpoint {
+ remote-endpoint = <&i2s2_cif_ep>;
+ };
+ };
+ xbar_i2s3_port: port at c {
+ reg = <0xc>;
+ xbar_i2s3_ep: endpoint {
+ remote-endpoint = <&i2s3_cif_ep>;
+ };
+ };
+ xbar_i2s4_port: port at d {
+ reg = <0xd>;
+ xbar_i2s4_ep: endpoint {
+ remote-endpoint = <&i2s4_cif_ep>;
+ };
+ };
+ xbar_i2s5_port: port at e {
+ reg = <0xe>;
+ xbar_i2s5_ep: endpoint {
+ remote-endpoint = <&i2s5_cif_ep>;
+ };
+ };
+ xbar_dmic1_port: port at f {
+ reg = <0xf>;
+ xbar_dmic1_ep: endpoint {
+ remote-endpoint = <&dmic1_cif_ep>;
+ };
+ };
+ xbar_dmic2_port: port at 10 {
+ reg = <0x10>;
+ xbar_dmic2_ep: endpoint {
+ remote-endpoint = <&dmic2_cif_ep>;
+ };
+ };
+ xbar_dmic3_port: port at 11 {
+ reg = <0x11>;
+ xbar_dmic3_ep: endpoint {
+ remote-endpoint = <&dmic3_cif_ep>;
+ };
+ };
+ };
+};
+
+&tegra_i2s1 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ i2s1_cif_ep: endpoint {
+ remote-endpoint = <&xbar_i2s1_ep>;
+ };
+ };
+ i2s1_port: port at 1 {
+ reg = <1>;
+ i2s1_dap_ep: endpoint {
+ dai-format = "i2s";
+ /* Placeholder for external Codec */
+ };
+ };
+ };
+};
+
+&tegra_i2s2 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ i2s2_cif_ep: endpoint {
+ remote-endpoint = <&xbar_i2s2_ep>;
+ };
+ };
+ i2s2_port: port at 1 {
+ reg = <1>;
+ i2s2_dap_ep: endpoint {
+ dai-format = "i2s";
+ /* Placeholder for external Codec */
+ };
+ };
+ };
+};
+
+&tegra_i2s3 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ i2s3_cif_ep: endpoint {
+ remote-endpoint = <&xbar_i2s3_ep>;
+ };
+ };
+ i2s3_port: port at 1 {
+ reg = <1>;
+ i2s3_dap_ep: endpoint {
+ dai-format = "i2s";
+ /* Placeholder for external Codec */
+ };
+ };
+ };
+};
+
+&tegra_i2s4 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ i2s4_cif_ep: endpoint {
+ remote-endpoint = <&xbar_i2s4_ep>;
+ };
+ };
+ i2s4_port: port at 1 {
+ reg = <1>;
+ i2s4_dap_ep: endpoint {
+ dai-format = "i2s";
+ /* Placeholder for external Codec */
+ };
+ };
+ };
+};
+
+&tegra_i2s5 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ i2s5_cif_ep: endpoint {
+ remote-endpoint = <&xbar_i2s5_ep>;
+ };
+ };
+ i2s5_port: port at 1 {
+ reg = <1>;
+ i2s5_dap_ep: endpoint {
+ dai-format = "i2s";
+ /* Placeholder for external Codec */
+ };
+ };
+ };
+};
+
+&tegra_dmic1 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ dmic1_cif_ep: endpoint {
+ remote-endpoint = <&xbar_dmic1_ep>;
+ };
+ };
+ dmic1_port: port at 1 {
+ reg = <1>;
+ dmic1_dap_ep: endpoint {
+ /* Placeholder for external Codec */
+ };
+ };
+ };
+};
+
+&tegra_dmic2 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ dmic2_cif_ep: endpoint {
+ remote-endpoint = <&xbar_dmic2_ep>;
+ };
+ };
+ dmic2_port: port at 1 {
+ reg = <1>;
+ dmic2_dap_ep: endpoint {
+ /* Placeholder for external Codec */
+ };
+ };
+ };
+};
+
+&tegra_dmic3 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ dmic3_cif_ep: endpoint {
+ remote-endpoint = <&xbar_dmic3_ep>;
+ };
+ };
+ dmic3_port: port at 1 {
+ reg = <1>;
+ dmic3_dap_ep: endpoint {
+ /* Placeholder for external Codec */
+ };
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
index 6a877de..0c917a1 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
@@ -6,6 +6,7 @@
#include <dt-bindings/mfd/max77620.h>
#include "tegra210.dtsi"
+#include "tegra210-audio-graph.dtsi"
/ {
model = "NVIDIA Jetson Nano Developer Kit";
@@ -870,4 +871,149 @@
vin-supply = <&vdd_5v0_sys>;
};
+
+ tegra_sound {
+ status = "okay";
+
+ compatible = "nvidia,tegra210-audio-graph-card";
+
+ dais = /* FE */
+ <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,
+ <&admaif4_port>, <&admaif5_port>, <&admaif6_port>,
+ <&admaif7_port>, <&admaif8_port>, <&admaif9_port>,
+ <&admaif10_port>,
+ /* Router */
+ <&xbar_i2s3_port>, <&xbar_i2s4_port>,
+ <&xbar_dmic1_port>, <&xbar_dmic2_port>,
+ /* I/O DAP Ports */
+ <&i2s3_port>, <&i2s4_port>,
+ <&dmic1_port>, <&dmic2_port>;
+
+ label = "jetson-nano-ape";
+ };
+};
+
+&tegra_admaif {
+ status = "okay";
+};
+
+&tegra_ahub {
+ status = "okay";
+
+ ports {
+ xbar_i2s3_port: port at c {
+ reg = <0xc>;
+ xbar_i2s3_ep: endpoint {
+ remote-endpoint = <&i2s3_cif_ep>;
+ };
+ };
+ xbar_i2s4_port: port at d {
+ reg = <0xd>;
+ xbar_i2s4_ep: endpoint {
+ remote-endpoint = <&i2s4_cif_ep>;
+ };
+ };
+ xbar_dmic1_port: port at f {
+ reg = <0xf>;
+ xbar_dmic1_ep: endpoint {
+ remote-endpoint = <&dmic1_cif_ep>;
+ };
+ };
+ xbar_dmic2_port: port at 10 {
+ reg = <0x10>;
+ xbar_dmic2_ep: endpoint {
+ remote-endpoint = <&dmic2_cif_ep>;
+ };
+ };
+ };
+};
+
+&tegra_i2s3 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ i2s3_cif_ep: endpoint {
+ remote-endpoint = <&xbar_i2s3_ep>;
+ };
+ };
+ i2s3_port: port at 1 {
+ reg = <1>;
+ i2s3_dap_ep: endpoint {
+ dai-format = "i2s";
+ /* Placeholder for external Codec */
+ };
+ };
+ };
+};
+
+&tegra_i2s4 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ i2s4_cif_ep: endpoint {
+ remote-endpoint = <&xbar_i2s4_ep>;
+ };
+ };
+ i2s4_port: port at 1 {
+ reg = <1>;
+ i2s4_dap_ep: endpoint at 0 {
+ dai-format = "i2s";
+ /* Placeholder for external Codec */
+ };
+ };
+ };
+};
+
+&tegra_dmic1 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ dmic1_cif_ep: endpoint at 0 {
+ remote-endpoint = <&xbar_dmic1_ep>;
+ };
+ };
+ dmic1_port: port at 1 {
+ reg = <1>;
+ dmic1_dap_ep: endpoint at 0 {
+ /* Placeholder for external Codec */
+ };
+ };
+ };
+};
+
+&tegra_dmic2 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ dmic2_cif_ep: endpoint at 0 {
+ remote-endpoint = <&xbar_dmic2_ep>;
+ };
+ };
+ dmic2_port: port at 1 {
+ reg = <1>;
+ dmic2_dap_ep: endpoint at 0 {
+ /* Placeholder for external Codec */
+ };
+ };
+ };
};
--
2.7.4
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