[PATCH v5 2/3] ASoC: dt-bindings: renesas, rz-ssi: Update slave dma channel configuration parameter
Biju Das
biju.das.jz at bp.renesas.com
Fri Aug 13 11:11:55 CEST 2021
The DMAC on RZ/G2L has specific slave channel configuration
parameters for SSI.
This patch updates the dmas description and example node to include
the encoded slave channel configuration.
Signed-off-by: Biju Das <biju.das.jz at bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
---
Note:-
This patch is based on [1]
[1]:- https://patchwork.kernel.org/project/linux-renesas-soc/patch/20210806095322.2326-2-biju.das.jz@bp.renesas.com/
v4->v5:
* Updated dmas description and removed fixes as it is an enhancement
now.
v3->v4:
* Updated bindings as the DMAC driver on RZ/G2L expects the
slave channel configuration to be passed in dmas property.
v2->v3:
* Merged the binding patch with dmas added
* Updated dt binding example with encoded #dma-cells value.
v1->v2:
* Rebased on 5.14-rc2.
---
.../bindings/sound/renesas,rz-ssi.yaml | 22 +++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml b/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml
index 471937cb8d05..414ff8035a4e 100644
--- a/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml
+++ b/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml
@@ -48,6 +48,24 @@ properties:
dmas:
minItems: 1
maxItems: 2
+ description:
+ The first cell represents a phandle to dmac
+ The second cell specifies the encoded MID/RID values of the SSI port
+ connected to the DMA client and the slave channel configuration
+ parameters.
+ bits[0:9] - Specifies MID/RID value of a SSI channel as below
+ MID/RID value of SSI rx0 = 0x256
+ MID/RID value of SSI tx0 = 0x255
+ MID/RID value of SSI rx1 = 0x25a
+ MID/RID value of SSI tx1 = 0x259
+ MID/RID value of SSI rt2 = 0x25f
+ MID/RID value of SSI rx3 = 0x262
+ MID/RID value of SSI tx3 = 0x261
+ bit[10] - HIEN = 1, Detects a request in response to the rising edge
+ of the signal
+ bit[11] - LVL = 0, Detects based on the edge
+ bits[12:14] - AM = 2, Bus cycle mode
+ bit[15] - TM = 0, Single transfer mode
dma-names:
oneOf:
@@ -93,8 +111,8 @@ examples:
clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
power-domains = <&cpg>;
resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
- dmas = <&dmac 0x255>,
- <&dmac 0x256>;
+ dmas = <&dmac 0x2655>,
+ <&dmac 0x2656>;
dma-names = "tx", "rx";
#sound-dai-cells = <0>;
};
--
2.17.1
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