[PATCH 3/8] ASoC: Intel: Skylake: Enable codec wakeup during chip init
Cezary Rojewski
cezary.rojewski at intel.com
Sun Nov 29 12:41:43 CET 2020
commit e603f11d5df8997d104ab405ff27640b90baffaa upstream.
Follow the recommendation set by hda_intel.c and enable HDMI/DP codec
wakeup during bus initialization procedure. Disable wakeup once init
completes.
Signed-off-by: Cezary Rojewski <cezary.rojewski at intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart at linux.intel.com>
Link: https://lore.kernel.org/r/20200305145314.32579-4-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie at kernel.org>
Cc: <stable at vger.kernel.org> # 5.4.x
---
sound/soc/intel/skylake/skl.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/sound/soc/intel/skylake/skl.c b/sound/soc/intel/skylake/skl.c
index f46b90ccb46f..1a3a3d6a3141 100644
--- a/sound/soc/intel/skylake/skl.c
+++ b/sound/soc/intel/skylake/skl.c
@@ -129,6 +129,7 @@ static int skl_init_chip(struct hdac_bus *bus, bool full_reset)
struct hdac_ext_link *hlink;
int ret;
+ snd_hdac_set_codec_wakeup(bus, true);
skl_enable_miscbdcge(bus->dev, false);
ret = snd_hdac_bus_init_chip(bus, full_reset);
@@ -137,6 +138,7 @@ static int skl_init_chip(struct hdac_bus *bus, bool full_reset)
writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV);
skl_enable_miscbdcge(bus->dev, true);
+ snd_hdac_set_codec_wakeup(bus, false);
return ret;
}
--
2.17.1
More information about the Alsa-devel
mailing list