[PATCH v2] ASoC: Intel: boards: eve: Fix DMIC records zero

[Pierre-Louis Bossart]

>>>>>     	case SND_SOC_DAPM_POST_PMD:
>>>>> -		clk_disable_unprepare(priv->mclk);
>>>>> -		clk_disable_unprepare(priv->sclk);
>>>>> +		if (__clk_is_enabled(priv->mclk))
>>>>> +			clk_disable_unprepare(priv->mclk);
>>>>> +
>>>>
>>>> [1] this seems wrong in case you have two SSPs working, and stop one.
>>>> This would turn off the mclk while one of the two SSPs is still working.
>>> For this platform we use either headset or dmic.
>>> There is no way we can record simultaneously using different devices.
>>> So disabling mclk might not be harmful here. But this case will always be true
>> too :).
>>
>> Maybe CRAS prevents you from recording on two inputs, but it looks like you
>> have independent front-ends so in theory couldn't you record at the alsa hw:
>> device level? Is this really mutually exclusive at the hardware level?
> True. Its not mutually exclusive at hardware level. the following might be safe
> if (!__clk_is_enabled(priv->sclk0)) &&  (!__clk_is_enabled(priv->sclk1))
> 	clk_disable_unprepare(priv->mclk);

I don't understand DAPM well-enough to know if these independent 
platform clock control routines are serialized by design or if this 
could be racy?