[PATCH 2/2] ASoC: Intel: Add period size constraint on strago board

[Takashi Iwai]

On Thu, 30 Jul 2020 17:27:58 +0200,
Pierre-Louis Bossart wrote:
> 
> 
> 
> >> Is this patch required if you've already constrained the period sizes for the
> >> platform driver in patch1?
> >
> > Yes or alsa will select 320 as default period size for it.
> 
> ok, then that's a miss in your patch1. 320 samples is a multiple of
> 1ms for 48kHz rates. I think it was valid only for the 16kHz VoIP
> paths used in some versions of Android, but that we don't support in
> the upstream code.
> 
> To build on Takashi's answer, the real ask here is to require that the
> period be a multiple of 1ms, because that's the fundamental
> design/limitation of firmware. It doesn't matter if it's 48, 96, 192,
> 240, 480, 960 samples.

If the 1ms alignment is the condition, it can be better with a
different hw_params constraint.  We can use
snd_pcm_hw_constraint_step() for such a purpose.


thanks,

Takashi