[PATCH 0/4] ASoC: fsl_asrc: allow selecting arbitrary clocks

[Nicolin Chen]

Hi Mark,

On Tue, Jul 14, 2020 at 09:27:53PM +0100, Mark Brown wrote:
> On Tue, Jul 14, 2020 at 01:15:45PM -0700, Nicolin Chen wrote:
> > On Tue, Jul 14, 2020 at 06:20:32PM +0200, Arnaud Ferraris wrote:
> 
> > > Here's some background about my use case: the i.MX6 board acts as a
> > > Bluetooth proxy between a phone and a headset. It has 2 Bluetooth
> > > modules (one for each connected device), with audio connected to SSI1 &
> > > SSI2. Audio sample rate can be either 8 or 16kHz, and bclk can be either
> > > 512 or 1024kHz, all depending of the capabilities of the headset and phone.
> > > In our case we want SSI2 to be the input clock to the ASRC and SSI1 the
> > > output clock, but there is no way to force that with auto-selection:
> > > both clocks are multiples of both 8k and 16k, so the algorithm will
> > > always select the SSI1 clock.
> 
> > Anything wrong with ASRC selecting SSI1 clock for both cases? The
> > driver calculates the divisors based on the given clock rate, so
> > the final internal rate should be the same. If there's a problem,
> > I feel that's a separate bug.
> 
> The nominal rate might be the same but if they're in different clock
> domains then the actual rates might be different (hence the desire for
> an ASRC I guess).  I can see the system wanting to choose one clock or
> the other on the basis of some system specific property (quality of the
> clock sources, tolerances of the devices involved or something) though
> it's a rather fun edge case configuration :/ .

Thanks for the input. Fox i.MX6, I don't feel it would be that
drastically different though. And both SSI1 and SSI2 can simply
select the same root clock source to avoid that happen.

Yet, in case that we need to support such an edge case, what's
a relatively common practice to allow system select the clock
source now?