[PATCH] ASoC: Intel: haswell: Power transition refactor

[Cezary Rojewski]

On 2020-04-06 17:02, Pierre-Louis Bossart wrote:
> On 4/6/20 3:48 AM, Cezary Rojewski wrote:
>> On 2020-03-30 21:45, Cezary Rojewski wrote:
>>> Update D0 <-> D3 sequence to correctly transition hardware and DSP core
>>> from and to D3. On top of that, set SHIM registers to their recommended
>>> defaults during D0 and D3 proceduces as HW does not reset registers for
>>> us.
>>>
>>> Connected to:
>>> [alsa-devel][BUG] bdw-rt5650 DSP boot timeout
>>> https://mailman.alsa-project.org/pipermail/alsa-devel/2019-July/153098.html 
>>>
>>>
>>> Github issue ticket reference:
>>> https://github.com/thesofproject/linux/pull/1842
>>>
>>> Tested on:
>>> - BDW-Y RVP with rt286
>>> - SAMUS with rt5677
>>>
>>> Proposed solution (both in July 2019 and on github):
>>> 'Revert "ASoC: Intel: Work around to fix HW d3 potential crash issue"'
>>> is NAKed as it only covers the problem up and actually brings back the
>>> undefined behavior: some registers (e.g.: APLLSE) are describing LPT
>>> offsets rather than WPT ones. In consequence, during power-transitions
>>> driver issues incorrect writes and leaves the regs of interest alone.
>>>
>>> Existing patch - the non-revert - does not resolve the HW D3 issue at
>>> all as it ignores the recommended sequence and does not initialize
>>> hardware registers as expected. And thus, leaving things as are is also
>>> unacceptable.
>>>
>>> Signed-off-by: Cezary Rojewski <cezary.rojewski at intel.com>
>>> ---
>>
>> Pierre, your thoughts on this? This has already been confirmed working.
> 
> I don't have any specific knowledge on Broadwell to comment. I also 
> haven't had time to test this patch, I was expecting Ross to provide his 
> Tested-by tag?

Hello,

Ross has provided his Tested-by tag already. Patch has been tested by 
Intel & Google side both. Given problem's impact, this fix is considered 
a critical one. I think we are good-to-go for quite a while now?

Czarek