[alsa-devel] [PATCH v2 11/12] ASoC: rt5677: Set ADC clock to use PLL and enable ASRC

[Curtis Malainey]

On Sun, Oct 20, 2019 at 1:38 PM Cezary Rojewski
<cezary.rojewski at intel.com> wrote:
>
> On 2019-10-18 22:04, Curtis Malainey wrote:
> > Use the PLL to kept the correct 24M clock rate so frequency shift does
> > not occur when using the DSP VAD.
> >
>
> > +static int bdw_rt5677_dsp_hw_params(struct snd_pcm_substream *substream,
> > +     struct snd_pcm_hw_params *params)
> > +{
> > +     struct snd_soc_pcm_runtime *rtd = substream->private_data;
> > +     struct snd_soc_dai *codec_dai = rtd->codec_dai;
> > +     int ret;
> > +
> > +     ret = snd_soc_dai_set_sysclk(codec_dai, RT5677_SCLK_S_PLL1, 24576000,
> > +             SND_SOC_CLOCK_IN);
> > +     if (ret < 0) {
> > +             dev_err(rtd->dev, "can't set codec sysclk configuration\n");
> > +             return ret;
> > +     }
> > +     ret = snd_soc_dai_set_pll(codec_dai, 0, RT5677_PLL1_S_MCLK,
> > +             24000000, 24576000);
> > +     if (ret < 0) {
> > +             dev_err(rtd->dev, "can't set codec pll configuration\n");
> > +             return ret;
>
> nitpick: you may skip "return ret" here and drop parenthesis as
> function's final line does the job.
>
> > +     }
> > +
> > +     return ret;
>
> If you decide to stick with leaving above as is, explicitly returning 0
> would be preferred.
>
fair enough, if there are no issues with the patch series I can follow
it up with a quick change to return 0.
>
> > +}