[alsa-devel] [PATCH v2 00/12] ASoC: tlv320aic32x4: Rework Clock Setting

[Annaliese McDermond]

The current tlv320aic32x4 code sets the various clock parameters by
looking in a static table in the kernel.  This works well enough,
but it has a few disadvantages.

1)  If the master clock doesn't match one of the precalculated values
    the driver cannot work.  This could be because the designer
    decided to use a different crystal, or because the clock comes
    from a PLL that can't quite achieve the proper frequency
    exactly.

2)  The driver only supports certain pre-calculated sample rates.
    The actual hardware can support many more.  These changes
    enable those rates.  Additionally, certain sample rates at
    certain clock rates were previously unavailable as
    combinations.

This patch dynamically calculates the various PLL and divider
values to find something that works.

Additionally, to enable much of this, the clock tree is
modeled as a part of the Common Clock Framework.  This allows
for easier debugigng as you can use the standard tools such as
/sys/kernel/debug/clk/clk_summary.  It also simplifies enabling
the entirety of the clock tree needed, and makes sure unused
clocks become disabled.

These patches have been tested and are working on a Raspberry Pi
with the simplecard driver.

Changes in v2:
 - Update 0002 patch to change Kconfig to add dependency on CCF
 - Update 0002 patch to correct the SPDX identifier
 - Update 0002 patch to use EXPORT_SYMBOL_GPL() instead of
   EXPORT_SYMBOL()
 - Update patches 0002, 0004 and 0005 to use prepare/unprepare
   instead of enable/disable since the i2c operations are not
   atomic
 - Update 0004 patch to fix indentation in commit message
 - Drop patch 0009 because it is a duplicate of the already
   committed patch in 667e9334
 - Update 0019 patch to keep aic32x4_set_dai_sysclk but to have
   it use clk_set_rate to set the master clock rate
 
Annaliese McDermond (12):
  ASoC: tlv320aic32x4: Break out clock setting into separate function
  ASoC: tlv320aic32x4: Model PLL in CCF
  ASoC: tlv320aic32x4: Model CODEC_CLKIN in CCF
  ASoC: tlv320aic32x4: Model DAC/ADC dividers in CCF
  ASoC: tlv320aic32x4: Model BDIV divider in CCF
  ASoC: tlv320aic32x4: Control clock gating with CCF
  ASoC: tlv320aic32x4: Move aosr and dosr setting to separate functions
  ASoC: tlv320aic32x4: Dynamically Determine Clocking
  ASoC: tlv320aic32x4: Restructure set_dai_sysclk
  ASoC: tlv320aic32x4: Remove mclk references
  ASoC: tlv320aic32x4: Propery Set Processing Blocks
  ASoC: tlv320aic32x4: Allow 192000 Sample Rate

 sound/soc/codecs/Kconfig             |   1 +
 sound/soc/codecs/Makefile            |   2 +-
 sound/soc/codecs/tlv320aic32x4-clk.c | 483 +++++++++++++++++++++++++++
 sound/soc/codecs/tlv320aic32x4.c     | 365 ++++++++++----------
 sound/soc/codecs/tlv320aic32x4.h     |  11 +
 5 files changed, 674 insertions(+), 188 deletions(-)
 create mode 100644 sound/soc/codecs/tlv320aic32x4-clk.c

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2.19.1