[alsa-devel] [RFC PATCH 1/4] alsa: make hw_params negotiation infrastructure 'bclk_ratio aware'

[Russell King - ARM Linux admin]

On Fri, Mar 08, 2019 at 01:10:57PM +0900, Takashi Sakamoto wrote:
> On Tue, Mar 05, 2019 at 09:23:46AM -0500, Sven Van Asbroeck wrote:
> > The original problem was that the fsl_ssi did not appear to work with the
> > tda998x hdmi codec. This codec seems to be 'unique' in the sense that it
> > needs to know the number of clocks per frame on the wire, i.e. the bclk_ratio,
> > which no-one in alsa is providing or using at the moment.
> > 
> > I first made the error of conflating the physical width and the bclk_ratio,
> > and posted this patch - Russell King quickly pointed out my error:
> > https://mailman.alsa-project.org/pipermail/alsa-devel/2019-February/145916.html
> > 
> > This then led to the following discussions:
> > https://mailman.alsa-project.org/pipermail/alsa-devel/2019-February/thread.html#145985
> > https://mailman.alsa-project.org/pipermail/alsa-devel/2019-February/thread.html#145947
> > 
> > Most of the discussion is about a mechanism to convey bclk_ratio from
> > the frame master
> > to the tda998x. We don't yet seem to have a consensus on how to do this best.
> > 
> > My rfc patch was only intended to provoke discussion, and to allow
> > people to experiment
> > with a flawed solution that would allow the alsa core to negotiate
> > bclk_ratio between
> > components. The uapi change is a serious flaw. bclk_ratio negotiation should be
> > invisible to userspace. But I cannot see a way to accomplish this.
> 
> In your case:
> 
> +---+            +-----+
> |CPU| <- wire -> |CODEC|
> |DAI|            | DAI |
> +---+            +-----+
> 
> So that:
> 
> CPU-DAI = fsl_ssi
> CODEC-DAI = tda998x
> wire = I2S
> 
> In I2S:
>  - SCK-line = serial clock
>  - WS-line = word select
>  - SD-line = serial data 
> 
> In general I2S communication:
>  - 2 samples are transferred in a phase of WS
> 
> In my opinion:
>  - 'the number of clocks per frame on the wire' (=you need)
>    = the number of phases of SCK per phase of WS
> 
> In expectation of ALSA PCM interface for hardware for usual device:
>  - half number of phases of SCK per phase of WC
>    = physical_width of sample
>    = bytes per sample

They are not the same thing.

Let's take SNDRV_PCM_FORMAT_S16_LE.  The in-memory layout of this format
is two 16-bit samples next to each other in a single 32-bit word.  Their
width is 16, their physical_width is 16, and bytes per sample is 2.

A CPU DAI can do one of two things:

1) it can generate exactly 16 SCK clock cycles per sample before WS
   changes state, leading to a total of 32 SCK clock cycles per
   frame.

2) it can generate more than 16 SCK clock cycles per sample.

Both are entirely legal and permissable under the I2S specification.
Both look the same in memory.

The ALSA format specification (SNDRV_PCM_FORMAT_*) does not specify
which of these two is used on the wire - it only specifies the in-
memory format.

If it were to specify the on-wire format, then we'd have to multiply
the number of in-memory formats by the number of on-wire formats.
These are (at least): AC'97, SPDIF, I2S(Philips), I2S(Left justified),
I2S(Right justified), two different DSP formats, and PDM.  Then for
at least the tree I2S modes, there are the number of SCK clocks per
sample which can be anything from the number of bits in the sample
up to an undefined limit.

What this means is that multiplying the number of in-memory formats
by the number of unboundable bus-specific formats leads to an
unboundable quantity of formats.

This is why ASoC has the ability to set the bclk (bit clock, SCK)
to sample rate ratio - in other words, the number of clocks to
completely transmit the samples for the number of channels on the
link - bit clock rate = sample rate * bclk_ratio.

-- 
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