[alsa-devel] [PATCH alsa-lib v4 3/4] ASoC: topology: Add definitions for mclk_direction values

[Kirill Marinushkin]

Current comment makes not clear the direction of mclk. Previously, similar
description caused a misunderstanding for bclk_master and fsync_master.

This commit solves the potential confusion the same way it is solved for
bclk_master and fsync_master.

Signed-off-by: Kirill Marinushkin <k.marinushkin at gmail.com>
Acked-by: Pierre-Louis Bossart <pierre-louis.bossart at linux.intel.com>
Cc: Jaroslav Kysela <perex at perex.cz>
Cc: Takashi Iwai <tiwai at suse.de>
Cc: Mark Brown <broonie at kernel.org>
Cc: Pan Xiuli <xiuli.pan at linux.intel.com>
Cc: Liam Girdwood <liam.r.girdwood at linux.intel.com>
Cc: alsa-devel at alsa-project.org
---
 include/sound/asoc.h |  6 +++++-
 include/topology.h   |  2 +-
 src/topology/pcm.c   | 15 +++++++++++++--
 3 files changed, 19 insertions(+), 4 deletions(-)

diff --git a/include/sound/asoc.h b/include/sound/asoc.h
index 297e837c..bb8aec78 100644
--- a/include/sound/asoc.h
+++ b/include/sound/asoc.h
@@ -140,6 +140,10 @@
 #define SND_SOC_TPLG_DAI_CLK_GATE_GATED	1
 #define SND_SOC_TPLG_DAI_CLK_GATE_CONT		2
 
+/* DAI mclk_direction */
+#define SND_SOC_TPLG_MCLK_CO            0 /* for codec, mclk is output */
+#define SND_SOC_TPLG_MCLK_CI            1 /* for codec, mclk is input */
+
 /* DAI physical PCM data formats.
  * Add new formats to the end of the list.
  */
@@ -330,7 +334,7 @@ struct snd_soc_tplg_hw_config {
 	__u8 invert_fsync;	/* 1 for inverted frame clock, 0 for normal */
 	__u8 bclk_master;	/* SND_SOC_TPLG_BCLK_ value */
 	__u8 fsync_master;	/* SND_SOC_TPLG_FSYNC_ value */
-	__u8 mclk_direction;    /* 0 for input, 1 for output */
+	__u8 mclk_direction;    /* SND_SOC_TPLG_MCLK_ value */
 	__le16 reserved;	/* for 32bit alignment */
 	__le32 mclk_rate;	/* MCLK or SYSCLK freqency in Hz */
 	__le32 bclk_rate;	/* BCLK freqency in Hz */
diff --git a/include/topology.h b/include/topology.h
index 3793115c..27da7308 100644
--- a/include/topology.h
+++ b/include/topology.h
@@ -1002,7 +1002,7 @@ struct snd_tplg_hw_config_template {
 	unsigned char  invert_fsync;    /* 1 for inverted frame clock, 0 for normal */
 	unsigned char  bclk_master;     /* SND_SOC_TPLG_BCLK_ value */
 	unsigned char  fsync_master;    /* SND_SOC_TPLG_FSYNC_ value */
-	unsigned char  mclk_direction;  /* 0 for input, 1 for output */
+	unsigned char  mclk_direction;  /* SND_SOC_TPLG_MCLK_ value */
 	unsigned short reserved;        /* for 32bit alignment */
 	unsigned int mclk_rate;	        /* MCLK or SYSCLK freqency in Hz */
 	unsigned int bclk_rate;	        /* BCLK freqency in Hz */
diff --git a/src/topology/pcm.c b/src/topology/pcm.c
index b53f6b03..2ce1651b 100644
--- a/src/topology/pcm.c
+++ b/src/topology/pcm.c
@@ -1223,8 +1223,19 @@ int tplg_parse_hw_config(snd_tplg_t *tplg, snd_config_t *cfg,
 			if (snd_config_get_string(n, &val) < 0)
 				return -EINVAL;
 
-			if (!strcmp(val, "master"))
-				hw_cfg->mclk_direction = true;
+			if (!strcmp(val, "master")) {
+				/* For backwards capability,
+				 * "master" == "for codec, mclk is input"
+				 */
+				SNDERR("warning: deprecated mclk value '%s'\n",
+				       val);
+
+				hw_cfg->mclk_direction = SND_SOC_TPLG_MCLK_CI;
+			} else if (!strcmp(val, "codec_mclk_in")) {
+				hw_cfg->mclk_direction = SND_SOC_TPLG_MCLK_CI;
+			} else if (!strcmp(val, "codec_mclk_out")) {
+				hw_cfg->mclk_direction = SND_SOC_TPLG_MCLK_CO;
+			}
 			continue;
 		}
 
-- 
2.13.6