[alsa-devel] [PATCH v3 2/2] ASoC: codec: wm8960: Relax bit clock computation

[Charles Keepax]

On Tue, Mar 21, 2017 at 05:03:25PM +0200, Daniel Baluta wrote:
> WM8960 derives bit clock from sysclock using BCLKDIV[3:0] of R8
> clocking register (See WM8960 datasheet, page 71).
> 
> There are use cases, like this:
> aplay -Dhw:0,0 -r 48000 -c 1 -f S20_3LE -t raw audio48k20b_3LE1c.pcm
> 
> where no BCLKDIV applied to sysclock can give us the exact requested
> bitclk, so driver fails to configure clocking and aplay fails to run.
> 
> Fix this by relaxing bitclk computation, so that when no exact value
> can be derived from sysclk pick the closest value greater than
> expected bitclk.
> 
> Suggested-by: Charles Keepax <ckeepax at opensource.wolfsonmicro.com>
> Signed-off-by: Daniel Baluta <daniel.baluta at nxp.com>
> ---

Acked-by: Charles Keepax <ckeepax at opensource.wolfsonmicro.com>

Thanks,
Charles