[alsa-devel] [PATCH 4/9] ASoC: sun8i-codec: Add support for A64 SoC

[Mark Brown]

On Wed, Dec 06, 2017 at 07:53:08PM +0100, Maxime Ripard wrote:
> On Wed, Dec 06, 2017 at 03:48:10PM +0000, Mark Brown wrote:

> > BCLK can be higher than the minimum there in most formats, though some
> > hardware is more restrictive so we tend to go for the minimum clock rate.

> How does that work in such a case? Is LRCK faster as well, and we're
> keeping the same ratio, or will the codec buffer the current sample
> until the next word?

No, the extra clock cycles just get ignored - most of the formats define
the location of the data in terms of LRCLK edges, any extra BCLK edges
shouldn't do anything.

> Is it usually a property of the codec or the DAI?

Things that require extra cycles for some reason tend to be CODECs, but
this can also be done just because whatever the clock master is doesn't
have very flexible dividers.
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