[alsa-devel] [PATCH v2 2/2] ASoC: wm8960: Let wm8960 driver configure its bit clock and frame clock

[Daniel Baluta]

<Removing Zidan from thread because the address no longer exists>

On Mon, Apr 3, 2017 at 4:54 PM, Charles Keepax
<ckeepax at opensource.wolfsonmicro.com> wrote:
> On Mon, Apr 03, 2017 at 04:39:40PM +0300, Daniel Baluta wrote:
>> On Mon, Apr 3, 2017 at 4:34 PM, Charles Keepax
>> <ckeepax at opensource.wolfsonmicro.com> wrote:
>> > On Mon, Apr 03, 2017 at 04:16:23PM +0300, Daniel Baluta wrote:
>> > Does this problem still remain after the relaxed clock
>> > computation? The maths you quote depends on the derived BCLK
>> > being exactly the correct speed for the audio, that is no longer
>> > the case anymore.
>> >
>> > I would have thought the patch would cover both situations, as in
>> > if we can produce a suitable LRCLK, then we just pick a BCLK we
>>
>> That!
>>
>> The problem for remaining rates is that we cannot derive the LRCLK
>>
>> <snip>
>> + for (j = 0; j < ARRAY_SIZE(dac_divs); ++j) {
>> + if (sysclk != dac_divs[j] * lrclk)
>> + continue;
>> </snip>
>>
>
> If you can't generate the LRCLK you either need a different
> source clock or to use the PLL. You don't want to be trying to
> pull 44.1k audio over a link that is clocked on a 48k based
> clock.

Yup, this makes sense to me.

>
> Is the problem here that the PLL part of the code is making the
> same assumption as the direct part of the code was, that the bclk
> should be exact?

Yes.


After wm8960_configure_sysclk fails to find a LRCLK, we try to use the
PLL.

Anyhow, here we don't even reach to check if the PLL can be used because
there is no solution for the following system:

freq_out = sysclk * sysclk_divs[i];
sysclk = lrclk * dac_divs[j];
sysclk == bclk * bclk_divs[k]


Perhaps, we can also try here to relax bitclk computation like we did for when
sysclk was directly derived from mclk.

thanks,
Daniel.