[alsa-devel] [PATCH] ASoC: adau: Factor out shared PLL configuration code

[Mark Brown]

On Thu, Jun 09, 2016 at 08:40:46PM +0200, Lars-Peter Clausen wrote:
> On 06/09/2016 07:41 PM, Mark Brown wrote:
> > On Thu, Jun 09, 2016 at 07:39:06PM +0200, Lars-Peter Clausen wrote:
> >> Multiple devices from the ADAU family share the same PLL structure and
> >> configuration register layout. Introduce a new helper module that can be
> >> used to calculated the PLL configuration registers based on a specified
> >> input frequency and the desired output frequency of the PLL.

> > Sounds like we may be heading towards an MFD with a clock driver here?

> Not at the moment, the PLL outputs are only used internally so it makes
> no sense to expose it through the CCF at the moment. The questions on
> IRC were more about how to replace the input clock configuration, which
> is currently done through the set_sysclk callbacks, with the CCF.

This was independant of the IRC discussion - it's just the pattern that
you're describing here.
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