[alsa-devel] [PATCH] ASoC: adau17x1: Cache writes when core clock is disabled

[Andreas Irestål]

On Thu, Feb 04, 2016 at 06:24:08PM +0100, Lars-Peter Clausen wrote:
> On 02/04/2016 06:22 PM, Lars-Peter Clausen wrote:
> [...]
> >> +	/* Enable cache only mode as we could miss writes before bias level
> >> +	 * reaches standby and the core clock is enabled */
> >> +	regcache_cache_only(regmap, true);
> >> +
> > 
> > There are a few register writes before this where the hardware configuration
> > is setup. When I look at my test setup those writes seem to go through, even
> > though they shouldn't according to what you say (and to what is written in
> > the datasheet).
> > 
> > On the other hand I've never seen the issue you are having either and I've
> > tested both master and slave configuration of the device. Maybe something
> > changed in the silicon in newer revisions of the device. Can you take a look
> > whether the hardware configuration is correctly applied for you?
> 
> Ah, no, ignore that. Those writes happen later on.
> 

The whole thing depends on what driver you are using. We had our own
board drivers before moving to DT, where we would call set_dai_fmt in
hw_params, so the register would get written again before we wanted to
do something useful anyway. The simple-card driver only set the dai format
at probing time and never again, so that's why we started to notice this
issue.

I posted a set of patches a few days ago which added DT support and
fixed minor things in adau17x1, but I realized I was clumsy just sending
it to the alsa-devel list and not including DT maintainers or any
maintainers at all. Would you have a look at it, or do you want me to
resubmit the patches with the correct recipents?

/Andreas