[alsa-devel] [PATCH 2/2] ASoC: nau8825: provide clock divide for codec mater mode

[Mark Brown]

On Tue, Dec 20, 2016 at 04:47:07PM +0800, John Hsu wrote:
> Provide the LRC and BCLK divide. The clock divide needs configuration
> properly when codec in master mode.

Why is the driver not able to configure these automatically, most
devices manage to do that OK?  Typically systems are fine with the
obvious divisions down from the root clock, the driver should at least
offer that as a default rather than requiring all machine drivers to
duplicate the divisor selection code.
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