[alsa-devel] fsl_ssi.c: Getting channel slips with fsl_ssi.c in TDM (network) mode.
Nicolin Chen
nicoleotsuka at gmail.com
Fri Oct 30 17:07:18 CET 2015
Add Shengjiu.
On Fri, Oct 30, 2015 at 09:45:32AM +0100, arnaud.mouiche at invoxia.com wrote:
> >At imx50 age, I remember one workaround was to fill the fifo
> >manually, writing directly a number of samples (equal to the
> >number of slots for one frame to keep the synchronization), and
> >then, enable the TMDAE.
> >This just allow to not have to wait an undefined period of time
> >for the DMA to be ready.
> >But, on the other hand, if the time to wait the DMA is short
> >enough, it should not be an issue.
> In the same idea, they were other similar issues to deal with
> concerning the RX and TX fifo.
>
> 1) Still some samples in the TX fifo when stoping/ re-starting the
> TX, while RX stream is going on.
> Since we can't reset the TX fifo content without disabling SSIEN,
> possible samples filled by the TX DMA are still there when the TX
> stream stops. And when we start it again, they introduce a random
> de-synchronization of the output.
> The workaround for this case was to add additional zero samples in
> the fifo manually to reach a multiple of the frame size.
> But I would prefer a way to empty manually the fifo instead. If
> Freescale can help us to find another way as they know the internal
> of the SSI...
>
> 2) the same for RX fifo, if the RX stream is stopped/-restarted,
> while TX stream is not stopped.
> We may still have some samples in the RX fifo, and those fifo must
> be removed before starting the RX again.
> This was more simple in this case, since we only need to read the RX
> register manually until the fifo is empty, before enabling the DMA.
>
> Obviously, disabling the SSIEN completely to start on good basis is
> not possible since we will lose a random number of samples already
> present in the fifo corresponding to the stream we don't want to
> stop, and this number of samples may not be a multiple of slots.
You are right. Since SSI doesn't have separate FIFO reset bits
for TX and RX respectively. These could be issues.
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