[alsa-devel] fsl_ssi.c: Getting channel slips with fsl_ssi.c in TDM (network) mode.

[Caleb Crome]

On Tue, Oct 27, 2015 at 9:45 AM, Fabio Estevam <festevam at gmail.com> wrote:
> On Tue, Oct 27, 2015 at 2:42 PM, Caleb Crome <caleb at crome.org> wrote:
>> On Tue, Oct 27, 2015 at 9:10 AM, Fabio Estevam <festevam at gmail.com> wrote:
>>> On Tue, Oct 27, 2015 at 2:02 PM, Caleb Crome <caleb at crome.org> wrote:
>>>
>>>>> Could you please try it without using the external SDMA firmware?
>>>>
>>>> I do need *some* SDMA firmware, correct?  The firmware that I'm using
>>>> ends up in /lib/firmware/imx/sdma/sdma-imx6q.bin and is md5sum
>>>> 5d4584134cc4cba62e1be2f382cd6f3a.
>>>
>>> SSI can operate with the ROM SDMA firmware.
>>>
>>> I would like to know if this issue also happens if you don't pass the
>>> external firmware and use the internal ROM SDMA firmware instead.
>>
>> Ah, good to know.  Do I just remove reference in the .dtsi file?
>> Remove the file from the filesystem?  I'll do both to be doubly sure
>> :-)
>
> Just remove it from the rootfs. Then you will see a message from the
> kernel saying that no external SDMA firmware could be found and that
> the internal one is going to be used.

I gave it a try.  No noticeable  change in behavior.

>
>>> Also, could you try bumping the SSI and SDMA clock rates at the maximum?
>>
>> Any idea how I do that?  I guess it's in the .dtsi file perhaps?  I'll
>> poke around.
>
> You can try to call clk_set_rate() with the maximum allowed frequency
> inside the ssi driver. I don't recall on top of my head what is this
> value though.

I don't know what to use as a parameter to clk_set_rate().  The 2
clocks that I see in the SDMA configuration are clk_ipg, and clk_ahb.
The IMX6SDLRM syas, "configurable clock options for the SDMA core and
the ARM platform DMA units.  1:2 ratio with maximum of SDMA core
running at ARM platform peripheral bus speed and DMS running at max
DMA frequency.  1:1 ratio when both SDMA core and ARM platform DMA
clocks are set to the ARM platform peripheral bus speed"

But, I have a hard time reconsiling that statement with the code in
sdma_init, which references only the ipg and ahb clocks.  I put in a
printk, and found the clk_ipg and clk_ahb to be 132 MHz.

The IMX6SDLRM.pdf, page 4717 says: "...but the SDMA core is physically
limited to a maximum 104 MHz frequency...".

So, I just don't know what clock to set to 104 MHz, or if the 104MHz
really is the right limit.  Any ideas?


This made me think that possibly the problem is with cpufreq
dynamically scaling the core frequency. So I tried:
echo performance > /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor
echo performance > /sys/devices/system/cpu/cpu1/cpufreq/scaling_governor

To ensure that the clocks don't dynamically switch on me, but I still
get channel slips.  Unfortunately,  it's hard to get statistical
measures with my eyeballs (watching a scope with TDM decode).  It
might be a little better, but still fails.

Thanks,
  -Caleb


>
> Regards,
>
> Fabio Estevam