[alsa-devel] [PATCH] ASoC: Document DAI signal polarity

[Benoît Thébaudeau]

Dear Anatol Pomozov,

On Fri, Oct 2, 2015 at 5:33 PM, Anatol Pomozov <anatol.pomozov at gmail.com> wrote:
> Currently there is no clear definition of what FSYNC polarity is.
> Different drivers use its own definition of what is "normal" and what is
> "inverted" fsync. This leads to compatibility problems between drivers.
>
> For example TegraX1 driver assumes that DSP-A format with frames
> starting at rising FSYNC edge has "inverted" polarity,
> while RT5677 assumes it is "normal" polarity.
>
> Explicitly specify meaning of BCLK/FSYNC polarity to avoid future
> compatibility problems.
>
> Signed-off-by: Anatol Pomozov <anatol.pomozov at gmail.com>
> ---
>  include/sound/soc-dai.h | 17 ++++++++++++++++-
>  1 file changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/include/sound/soc-dai.h b/include/sound/soc-dai.h
> index 2df96b1..91e2e61 100644
> --- a/include/sound/soc-dai.h
> +++ b/include/sound/soc-dai.h
> @@ -48,10 +48,25 @@ struct snd_compr_stream;
>  #define SND_SOC_DAIFMT_GATED           (0 << 4) /* clock is gated */
>
>  /*
> - * DAI hardware signal inversions.
> + * DAI hardware signal polarity.
>   *
>   * Specifies whether the DAI can also support inverted clocks for the specified
>   * format.
> + *
> + * BCLK:
> + * - "normal" polarity means signal is available at rising edge of BCLK
> + * - "inverted" polarity means signal is available at falling edge of BCLK
> + *
> + * FSYNC "normal" polarity depends on the frame format:
> + * - I2S: frame consists of left then right channel data. Left channel starts
> + *      with falling FSYNC edge, right channel starts with rising FSYNC edge.
> + * - Left/Right Justified: frame consists of left then right channel data.
> + *      Left channel starts with rising FSYNC edge, right channel starts with
> + *      falling FSYNC edge.
> + * - DSP A/B: Frame starts with rising FSYNC edge.
> + * - AC97: Frame starts with rising FSYNC edge.
> + *
> + * "Negative" FSYNC polarity is the one opposite of "normal" polarity.
>   */
>  #define SND_SOC_DAIFMT_NB_NF           (0 << 8) /* normal bit clock + frame */
>  #define SND_SOC_DAIFMT_NB_IF           (2 << 8) /* normal BCLK + inv FRM */
> --
> 2.6.0.rc2.230.g3dd15c0
>

Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau.dev at gmail.com>

Best regards,
Benoît