[alsa-devel] [PATCH v1 1/5] ASoC: rockchip: i2s: Support to set the divider clock API

[Caesar Wang]

Hi  Mark,

Very responsive, thanks your comment.

在 2015年11月06日 00:16, Mark Brown 写道:
> On Thu, Nov 05, 2015 at 01:56:39PM +0800, Caesar Wang wrote:
>> 在 2015年11月04日 22:34, Mark Brown 写道:
>>> Same thing as your other very similar patch: why does this feature
>>> require set_clkdiv()?
>> Okay, you said "
>> Why is this a requirement?  The clock to use as a source should normally
>> be specified via set_sysclk() and any internal dividers calculated
>> automatically by the driver.
>> "
>> I think we should divider settings for these different sample rates.
> Sure, the question is how these things get set.
>
>>   If the codec is master mode, we are *not* need this operate.
>>   If the codec is slave mode, we are need to divider the MCLK to setting the different sample rates.
>> (for example, the sample rates (8k, 48k) the clock is MCLK, the clock should be divider cpu ip )
>> "dividers calculated automatically by the driver", that should be occured by codec(max98090
>> ) driver, but the divider clocks (LRCK, SCLK) should need to set for cpu internal side.
> So the CPU knows what rates it needs to set and what clocks it's getting
> in, why can't it set the dividers autonomously.

Sound resonable,  fixed in next version.

>
>
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-- 
caesar wang | software engineer | wxt at rock-chip.com