[alsa-devel] Can iMX6SL supports different sampling rate for different SSIs?

[Xuebing Wang]

Nicolin,

Thank you very much for your always help.

I am using 3 SSIs (as I2S master mode) on iMX6SL for 3 different codec.

1) If I read iMX6SL reference manual correctly, I am deriving SSI 
sys_clock from pll4.

-- pll4 = Fref * (DIV_SELECT + NUM/DENOM)
    ** I am using a value of 786.432000 MHz

-- pll4_main_clk = pll4 / (PLL_AUDIOn: POST_DIV_SELECT) / 
CCM_ANALOG_MISC2n: MSB:LSB
    ** I am using a value of 196.608 MHz

-- SSI1_CLK_ROOT = pll4_main_clk / (CS1CDR: ssi1_clk_pred) / CS1CDR: 
ssi1_clk_podf
    ** I am using a value of 3.072 MHz (for 48k sampling rate)


2) As pll4_main_clk is global for all 3 SSIs, I think that we can *not* 
use 8k for ssi1 and 44.1k for ssi2, right? Because 8k and 44.1k requires 
different pll4 clock, right?
     -- However, as 48k, 32k, 16k, 8k can use same pll4, thus different 
SSI can use different sampling rate in this subset (48k, 32k, 16k, 8k).
     -- Same principle applies for 44.1k, 22.050, 11.025 subset of 
sampling rates.

Is my understanding correct?


-- 
Xuebing