[alsa-devel] [PATCH] ASoC: wm8960: update pll and clock setting function

[Charles Keepax]

On Fri, Jun 26, 2015 at 07:09:22PM +0800, Zidan Wang wrote:
> When using snd_soc_dai_set_pll to set pll in machine driver, we
> should set pll in and pll out freq and ensure 5 < PLLN < 13,
> otherwise set pll will be failed. In order to support more
> formats and sample rates for a certain MCLK, if snd_soc_dai_set_pll
> failed, it will calculate a available pll out freq and set the pll
> again.
> 
> Signed-off-by: Zidan Wang <zidan.wang at freescale.com>
> ---

I think this need a little more explaination on how this is
expected to work. From looking at the code what it looks like
what happens is you can set a PLL frequency through set_pll but
then if that frequency doesn't support the sample rate requested
through hw_params it will be changed. This makes me a little
nervous, as something explicitly requested is being overwritten
automatically.

Would it perhaps be better to allow the auto selection of the
PLL frequency only when things haven't been manually set, or
provide some setting that indicates auto mode?

Thanks,
Charles