[alsa-devel] [PATCH 4/4] sound: jz4740: Enable codec clock during dai_probe

[Lars-Peter Clausen]

On 01/26/2015 12:30 PM, Zubair Lutfullah Kakakhel wrote:
>
> On 26/01/15 10:40, Lars-Peter Clausen wrote:
>> On 01/26/2015 11:18 AM, Zubair Lutfullah Kakakhel wrote:
>>> As we are moving away from platform to DT, we cant rely on the board
>>> file to do this now. So enable it here.
>>
>> I don't understand this changelog. The board file never did this. The driver enables the clock in the startup() callback.
>
> My bad.
>
> I couldn't get the ci20 audio to work without this change.
>
> I double checked. The clock is indeed enabled.
>
> But the rate needs to be set for the ci20.
>
> clk_set_rate(i2s->clk_i2s, 12000000);
>
> Where should I put it? I couldn’t trace how the rate is set for the jz4740..

There is no support for specifying clock rate defaults in the devicetree 
itself. See commit 86be408bfbd8 ("clk: Support for clock parents and rates 
assigned from device tree"). Since the preferred or correct clock rate will 
be board specific this is probably where it should go.

- Lars