[alsa-devel] What is exact definition of "normal/inverted" FSYNC signal polarity?

[Anatol Pomozov]

Hi

Thanks.

On Mon, Aug 31, 2015 at 11:02 AM, Mark Brown <broonie at kernel.org> wrote:
> The simplest thing to do is look at the datasheets for Wolfson parts
> like the wm8731, they have some very clear diagrams of all the data
> modes we support.

I looked at http://www.rockbox.org/wiki/pub/Main/DataSheets/WM8731_8731L.pdf
spec and it is what I see

"normal" bitclock means data sensing happens at rising edge of BCLK.
It is the same as TegraX1 and rt5677 examples above.

As of FSYNC - the wm8731 driver uses Reg0x7[4] to set FSYNC polarity.
If FSYNC is inverted then bit set to 1. According to the spec:

DACLRC phase control (in left, right or I2S modes)
1 = Right Channel DAC data when DACLRC high
0 = Right Channel DAC data when DACLRC low
(opposite phasing in I2S mode)
or
DSP mode A/B select (in DSP mode only)
1 = MSB is available on 2nd BCLK rising edge after DACLRC rising edge
0 = MSB is available on 1st BCLK rising edge after DACLRC rising edge


Thus "normal" FSYNC for this driver means that the frame (L channel)
starts at rising edge of FSYNC (wm8731 datasheet calls it DACLRC).
"inverted" means frame starts at the falling edge. It differs both
from TegraX1 and rt5677 above.

For TDM mode A the chip seems always expect to see "normal" polarity
FSYNC (frame starts at rising edge of FSYNC).




It looks like each driver uses its own definition of FSYNC polarity.
To avoid compatibility problems between different codecs/socs there
should be a clean definition of what is FSYNC polarity is. I would
propose something simple like:
    ****  "normal" FSYNC means frame starts at rising edge of FSYNC,
and "inverted" frame starts at falling FSYNC edge ****
i.e. the same as for 8731.