[alsa-devel] What is exact definition of "normal/inverted" FSYNC signal polarity?

[Anatol Pomozov]

Hi

I am trying to configure TegraX1 SoC and Realtek5677 codec. These two
drivers have different meaning of FSYNC polarity in TDM mode A format.

* TegraX1 driver thinks that "normal" polarity is when a frame starts
with FSYNC falling edge. TegraX1 applies it to all formats (I2S,
PCM/TDM mode A). And inverted FSYNC means that frame starts with
rising edge of FSYNC.

* RT5677 thinks that "normal" for I2S is "frame starts with falling
edge". And for TMD mode A "normal" means "frame starts with rising
FSYNC edge".

Thus normal/inverted FSYNC in TDM mode A are opposite at these 2
chips. Which one is correct? What is exact definition of
SND_SOC_DAIFMT_xB_yF constants in soc-dai.h?

I tried to google if I2S spec [1] defines FSYNC polarity but no luck.

It worth to clarify definition of BCLK polarity as well. I believe
"normal" BCLK is "line sensing happens at rising edge", "inverted"
BCLK - "line sensing happens at falling edge". Is it correct?

[1] https://web.archive.org/web/20060821114007/http://www.semiconductors.philips.com/acrobat_download/various/I2SBUS.pdf