[alsa-devel] [RFC 6/7] ASoC: hda: Add support for SSP register settings

[Pierre-Louis Bossart]

On 4/27/15 9:15 AM, Mark Brown wrote:
> On Sun, Apr 26, 2015 at 07:48:31PM +0530, Vinod Koul wrote:
>> On Fri, Apr 24, 2015 at 06:55:32PM +0100, Mark Brown wrote:
>
>>>> +		/* Dont add odd number of dummy bits, since I2S requires
>>>> +		 * dummy bit after each slot/channel
>>>> +		 */
>
>>> It does?
>
>> For us unfortuntely yes. We send 24 bit audio to codec and clock divider
>> doesn't give us 48clocks per frame, so we have to add dummy clocks in each
>> slot and send 25 clocks per slot
>
> So it's the hardware rather than I2S itself :)

It depends on the clock reference used to drive the SSP. With a 19.2 
reference we typically divide by 50 and pad with a trailing bit.

That said I am not sure how this code would work on SKL. Vinod, isn't 
this for BXT only? how do you get 19.2 on SKL, shouldn't you guys use a 
24 MHz root frequency to find the divider?