[alsa-devel] [PATCH] ASoC: sgtl5000: Allow the codec to work in slave mode

[Michael Trimarchi]

Hi Mark

On Tue, Sep 30, 2014 at 9:29 PM, Mark Brown <broonie at kernel.org> wrote:
> On Mon, Sep 29, 2014 at 10:17:57AM -0300, Fabio Estevam wrote:
>> On Mon, Sep 22, 2014 at 10:54 PM, Mark Brown <broonie at kernel.org> wrote:
>
>> > Are you sure that the configuration that results is valid?  Typically
>> > the requirements for MCLK to other clock ratios are very similar for
>> > master and slave modes, it's just that it tends to be a lot more obvious
>> > when things go wrong in master mode since directly visible clocks tend
>> > to go wrong as opposed to performance problems.  Are the dividers that
>> > we can't get configuration for purely for generating BCLK/LRCLK in
>> > master mode or are they for other things?
>
>> Tested sgtl5000 slave mode with different sampling rates and it plays well.
>
>> Any particular register I should monitor?
>
> Did you just listen or did you measure the performance?
>
>> Sorry, but I guess I did not understand your last question.
>
> I'm really not sure how to simplify it...  clearly we're skipping some
> configuration here, what does it do - is it purely for generating BCLK
> and LRCLK?

Are you talking about clock_in and sigma-delta? So no  the bclk and lrclk but
the clkin of the codec.

Michael

>
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| Michael Nazzareno Trimarchi                     Amarula Solutions BV |
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