[alsa-devel] [PATCH] ASoC: sgtl5000: Allow the codec to work in slave mode

[Fabio Estevam]

Hi Mark,

On Mon, Sep 22, 2014 at 10:54 PM, Mark Brown <broonie at kernel.org> wrote:
> On Thu, Sep 18, 2014 at 08:17:25PM -0300, Fabio Estevam wrote:
>
>>       default:
>> -             /* if mclk not satisify the divider, use pll */
>> +             /* if mclk not satisfy the divider, use pll */
>>               if (sgtl5000->master) {
>>                       clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
>>                               SGTL5000_MCLK_FREQ_SHIFT;
>> -             } else {
>> -                     dev_err(codec->dev,
>> -                             "PLL not supported in slave mode\n");
>> -                     return -EINVAL;
>>               }
>>       }
>
> Are you sure that the configuration that results is valid?  Typically
> the requirements for MCLK to other clock ratios are very similar for
> master and slave modes, it's just that it tends to be a lot more obvious
> when things go wrong in master mode since directly visible clocks tend
> to go wrong as opposed to performance problems.  Are the dividers that
> we can't get configuration for purely for generating BCLK/LRCLK in
> master mode or are they for other things?

Tested sgtl5000 slave mode with different sampling rates and it plays well.

Any particular register I should monitor?

Sorry, but I guess I did not understand your last question.