[alsa-devel] [PATCH v4] ASoC: sgtl5000: Fix the cache handling

[Mark Brown]

On Mon, May 26, 2014 at 09:26:33AM +0200, Lars-Peter Clausen wrote:

> I think the issue with this chip is that it wants a special sequence in
> which the registers are written when syncing the cache to the hardware. The
> first thing to check is probably if that is actually necessary. If not just
> drop the whole restore_regs thing. If it is necessary its probably worth
> investigating whether it makes sense to support custom sync sequences in
> regmap. We already have regcache_sync_region() so maybe add a
> regcache_sync_regions() which takes a array of struct regmap_range. And
> syncs the registers in the order of the ranges.

There's a few devices which need some sequencing on restore but it's
usually just for a very small subset of registers (and sometimes need
delays between the writes and things) so what tends to happen is a short
open coded sequences that do the ordering sensitive portions of the
sequence followed by a regcache_sync() which covers everything else.
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