[alsa-devel] twl4030 latency update

[Leonardo Gabrielli]

On 26/03/2014 09:26, Peter Ujfalusi wrote:
> The McBSP2 FIFO will be always there. There's nothing can be done on that. The
> size on McBSP2 is 1280 words -> 640 stereo samples, ie ~29ms with 22050,
> 14.5ms with 44100.
>
> If you are staying in element mode this means that it is granted that the
> sample at the DMA pointer will out on the i2s line about the mentioned times.
> This is the delay caused by the FIFO itself. From where the rest is coming I'm
> not really sure.
BTW: I forgot to mention: the latency listed in my previous email is 
input+output (i.e. I record pulses from the beagleboard input jack and 
the delayed version to the beagleboard output jack). The twl4030 analog 
and digital loopback features have been of course disabled, in order to 
get the total latency due from A/D to D/A.

So just to get confirm I understood the McBSP mechanism well: even 
though I can transfer to/from DMA samples in bursts of <threshold> 
length, each sample will always "travel along" the whole FIFO buffer 
length, (as if in a delay line) and thus they will always have 
640samples delay?

Would it be possible to workaround this, e.g. by putting 4-channel audio 
frames instead of stereo frames in the FIFO (with 2 channels unused), in 
order to fill up the FIFO more quickly and have less latency? Or is it 
pure craze?

Cheers and thank you