[alsa-devel] r8a7790 only has audio when clock is forced on

[Violeta Menendez Gonzalez]

Hi all,

We have a problem where audio on r8a7790 is not working due to it not 
sending interrupts.

We've verified that the pins and the clocks are working and correctly 
configured. The codec is starting and producing correct bit and word 
clock signals

We've made a hack to force /mstp10_clks /on that makes the audio work. 
Further investigation showed that it's only needed to force SSI(ALL) on, 
but, as far as we know, the manual doesn't say anything about it having 
to be kept on.

We've also debugged this hack and saw that the registers have correct 
values. These are some of the debugging messages we have when the audio 
fails:


Playing WAVE '../audio/r.wav' : Signed 16 bit Little Endian, Rate 44100 
Hz, Stereo
cpg_mstp_clock_endisable: index 5, enable 1
cpg_mstp_clock_endisable: index 5, value read from group->smstpcr 0002ffe0
cpg_mstp_clock_endisable: index 5, value write in group->smstpcr 0002ffc0
cpg_mstp_clock_endisable: index 15, enable 1
cpg_mstp_clock_endisable: index 15, value read from group->smstpcr 0002ffc0
cpg_mstp_clock_endisable: index 15, value written in group->smstpcr 00027fc0
aplay: pcm_writecpg_mstp_clock_endisable: index 15, enable 0
cpg_mstp_clock_endisable: index 15, value read from group->smstpcr 00027fc0
cpg_mstp_clock_endisable: index 15, value write in group->smstpcr 0002ffc0
:1710: write errcpg_mstp_clock_endisable: index 5, enable 0
cpg_mstp_clock_endisable: index 5, value read from group->smstpcr 0002ffc0
cpg_mstp_clock_endisable: index 5, value write in group->smstpcr 0002ffe0
or: Input/output error

This shows that the SSI (ALL) clock in bit 5 being enabled before the 
SSI0 and that it is also disabled in the reverse sequence as expected.

Not sure what to do next or what the problem could be.
Any new ideas are welcome,

Thanks!

-- 
Violeta Menéndez González	http://www.codethink.co.uk/
Software Engineer		Codethink - Providing Genius