[alsa-devel] [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

[Mark Brown]

On Fri, Jan 17, 2014 at 07:44:02PM +0100, Florian Meier wrote:
> On 01/17/2014 07:33 PM, Mark Brown wrote:

> > Setting it to false increases power consumption since the device is
> > kept more powered on when idle but reduces startup time from idle.  For
> > digital only devices like the wm8804 there shouldn't be any reason to
> > keep it powered up when not in use, the startup time is generally
> > negligable anyway.

> So a better solution would be to set SND_SOC_BIAS_OFF instead of
> SND_SOC_BIAS_STANDBY at the end of probe?

Yes (making sure that it is actually in that state).
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