[alsa-devel] I2S frame configuration

[Lars-Peter Clausen]

On 12/09/2014 02:51 PM, thomas chen wrote:
>
> I have set up according to the thread.... but when I attempt to play a sound
> file (with aplay)
> the program just stop ....
[...]
>
> Seems like the something (maybe clock ?) is missing ???

Yes, most likely your SoC is not seeing the frameclock/bitclock.

>
> Thx
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> On 12/8/2014 2:37 PM, Lars-Peter Clausen wrote:
>> On 12/08/2014 07:03 PM, thomas chen wrote:
>>>
>>> Thanks for the info... so it is possible for Asoc to handle such format...
>>
>> Yes, its not a special format, it is just plain and simple I2S like it is
>> supported by the majority of all drivers/devices.
>>
>>>
>>> So where does one specify number of bits in a FRAME/WORD (epsecially if we
>>> were to be master instead of slave ?)
>>
>> That's typically specified in the format that is used, e.g. in your case
>> SNDRV_PCM_FORMAT_S24_3LE. This is not necessarily ideal for all cases, but
>> has work well enough so far.
>>
>>>
>>> and, how does one specify number of bits to ignore (before the valid data)
>>
>> There are no bits to ignore the valid data. I2S has a delay of 1 bit clock
>> cycle between the first bit of the sample and the frame sync signal. So
>> the data bit that is transmitted on the same clock cycle as the frame sync
>> is actually the last bit of the previous sample. So in your case your
>> sample has 16 valid bits followed by 8 ignored bits.
>>
>>>
>>> and also how many valid bits (ie size of data word) ???
>>
>> You can set a snd_pcm_hw_constraint_msbits() constraint to tell userspace
>> that only a certain amount of bits are actually going to be used.
>>
>> If you are using ASoC you can do this by setting the sig_bits property on
>> your snd_soc_dai_driver.
>>
>> - Lars
>>
>>>
>>> Thanks...
>>>
>>>
>>>
>>>
>>> On 12/8/2014 12:01 PM, Clemens Ladisch wrote:
>>>> thomas chen wrote:
>>>>> I am working on a ALSA interface to a particular codec over I2S
>>>>>
>>>>> the audio stream format is a bit peculiar...
>>>>>
>>>>> there are 24 BCLK cycle between transition of FSYNC... howver, there
>>>>> are only 16 bit that are valid
>>>>>
>>>>> bit 0: ignore
>>>>> bit 1-16:   valid pcm data (MSB....LSB)
>>>>> bit 17-23: ignore
>>>> This is the 'original' I²S format.  The format where the sample begins
>>>> with the 1st BCLK usually is called left-justified (and uses the
>>>> opposite FSYNC polarity).
>>>>
>>>> Having ignored bits is common.  (Typically, there are 32 BCLK cycles per
>>>> sample.)
>>>>
>>>> In ASoC, this would be SND_SOC_DAIFMT_I2S and SND_SOC_DAIFMT_LEFT_J.
>>>>
>>>>
>>>> Regards,
>>>> Clemens
>>>
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>>
>