[alsa-devel] I2S frame configuration

[Clemens Ladisch]

thomas chen wrote:
> I am working on a ALSA interface to a particular codec over I2S
>
> the audio stream format is a bit peculiar...
>
> there are 24 BCLK cycle between transition of FSYNC...   howver, there are only 16 bit that are valid
>
> bit 0: ignore
> bit 1-16:   valid pcm data (MSB....LSB)
> bit 17-23: ignore

This is the 'original' I²S format.  The format where the sample begins
with the 1st BCLK usually is called left-justified (and uses the
opposite FSYNC polarity).

Having ignored bits is common.  (Typically, there are 32 BCLK cycles per
sample.)

In ASoC, this would be SND_SOC_DAIFMT_I2S and SND_SOC_DAIFMT_LEFT_J.


Regards,
Clemens